Search

Min Huang

Examiner (ID: 15733, Phone: (571)270-5798 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1007
Issued Applications
880
Pending Applications
58
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19618894 [patent_doc_number] => 20240404574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => FAST BACKGROUND ARRAY PATTERN WRITING [patent_app_type] => utility [patent_app_number] => 18/678630 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678630
FAST BACKGROUND ARRAY PATTERN WRITING May 29, 2024 Pending
Array ( [id] => 20367096 [patent_doc_number] => 20250356908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE [patent_app_type] => utility [patent_app_number] => 18/663115 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663115
Dynamic random-access memory (DRAM) device May 13, 2024 Issued
Array ( [id] => 19661782 [patent_doc_number] => 20240428847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => MEMORY DEVICE AND A DRIVING METHOD OF A SENSING DEVICE INCLUDED IN THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/661809 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661809
Memory device and a driving method of a sensing device included in the memory device May 12, 2024 Issued
Array ( [id] => 20704042 [patent_doc_number] => 12626757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Low-latency multiplexed pipeline memory [patent_app_type] => utility [patent_app_number] => 18/652651 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1279 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652651
Low-latency multiplexed pipeline memory Apr 30, 2024 Issued
Array ( [id] => 19384347 [patent_doc_number] => 20240274217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/645398 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645398
SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME Apr 24, 2024 Pending
Array ( [id] => 20311768 [patent_doc_number] => 20250329397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => SUB-BLOCK PROTECTION FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/639504 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639504
SUB-BLOCK PROTECTION FOR MEMORY DEVICES Apr 17, 2024 Pending
Array ( [id] => 19589385 [patent_doc_number] => 20240386942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SEMICONDUCTOR DEVICE HAVING PAD ELECTRODE EQUIPPED WITH LOW PASS FILTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/635854 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635854
Semiconductor device having pad electrode equipped with low pass filter circuit Apr 14, 2024 Issued
Array ( [id] => 20291069 [patent_doc_number] => 20250316312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/628554 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628554
Electronic device Apr 4, 2024 Issued
Array ( [id] => 20624761 [patent_doc_number] => 12592273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Usage-based disturbance mitigation [patent_app_type] => utility [patent_app_number] => 18/624920 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624920
Usage-based disturbance mitigation Apr 1, 2024 Issued
Array ( [id] => 19500154 [patent_doc_number] => 20240339172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS [patent_app_type] => utility [patent_app_number] => 18/624720 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624720
ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS Apr 1, 2024 Pending
Array ( [id] => 20581193 [patent_doc_number] => 12573447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/623041 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623041
Memory system Mar 31, 2024 Issued
Array ( [id] => 20237569 [patent_doc_number] => 20250294888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => STACKED MEMORY PHYSICAL LAYER (PHY) FLOORPLAN [patent_app_type] => utility [patent_app_number] => 18/608440 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608440
STACKED MEMORY PHYSICAL LAYER (PHY) FLOORPLAN Mar 17, 2024 Pending
Array ( [id] => 20806052 [patent_doc_number] => 12670964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Apparatus and method for changing a read voltage applied for reading data from a non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 18/604519 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13149 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604519
Apparatus and method for changing a read voltage applied for reading data from a non-volatile memory cell Mar 13, 2024 Issued
Array ( [id] => 19452376 [patent_doc_number] => 20240312506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/599986 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599986
Memory device Mar 7, 2024 Issued
Array ( [id] => 20468299 [patent_doc_number] => 12524338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Apparatus and methods for programming data states of memory cells [patent_app_type] => utility [patent_app_number] => 18/595703 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 18179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595703
Apparatus and methods for programming data states of memory cells Mar 4, 2024 Issued
Array ( [id] => 20210055 [patent_doc_number] => 20250279775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => GATING-BASED RECEIVER AND GATING SIGNAL GENERATOR [patent_app_type] => utility [patent_app_number] => 18/593970 [patent_app_country] => US [patent_app_date] => 2024-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593970
Gating-based receiver and gating signal generator Mar 2, 2024 Issued
Array ( [id] => 19467653 [patent_doc_number] => 20240321323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/589351 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589351
Memory device Feb 26, 2024 Issued
Array ( [id] => 20540206 [patent_doc_number] => 12557293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Ferroelectric memory device using back-end-of-line (BEOL) thin film access transistors and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/586444 [patent_app_country] => US [patent_app_date] => 2024-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586444
Ferroelectric memory device using back-end-of-line (BEOL) thin film access transistors and methods for forming the same Feb 23, 2024 Issued
Array ( [id] => 20636584 [patent_doc_number] => 12597465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/585056 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/585056
Memory device Feb 22, 2024 Issued
Array ( [id] => 20002080 [patent_doc_number] => 20250140302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICE FOR BOOSTING POWER PROVIDED TO CORE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/584918 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584918
Semiconductor device for boosting power provided to core circuit Feb 21, 2024 Issued
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