Search

Min Huang

Examiner (ID: 3981)

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
991
Issued Applications
867
Pending Applications
55
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19796076 [patent_doc_number] => 12237041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor memory device, memory system, and method [patent_app_type] => utility [patent_app_number] => 18/180707 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22815 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180707
Semiconductor memory device, memory system, and method Mar 7, 2023 Issued
Array ( [id] => 20389097 [patent_doc_number] => 12488830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Output timing for channel loopback of a memory device [patent_app_type] => utility [patent_app_number] => 18/117829 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/117829
Output timing for channel loopback of a memory device Mar 5, 2023 Issued
Array ( [id] => 20243944 [patent_doc_number] => 12424274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory device and manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/110321 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 2405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110321
Memory device and manufacturing thereof Feb 14, 2023 Issued
Array ( [id] => 20469225 [patent_doc_number] => 12525267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Device and method with computational memory [patent_app_type] => utility [patent_app_number] => 18/108737 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108737 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108737
Device and method with computational memory Feb 12, 2023 Issued
Array ( [id] => 19444254 [patent_doc_number] => 12094540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Non-volatile memory device and memory system including the same and program method thereof [patent_app_type] => utility [patent_app_number] => 18/103754 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14894 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103754
Non-volatile memory device and memory system including the same and program method thereof Jan 30, 2023 Issued
Array ( [id] => 18712545 [patent_doc_number] => 20230335178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Word Line Delay Interlock Circuit for Write Operation [patent_app_type] => utility [patent_app_number] => 18/158489 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158489
Word line delay interlock circuit for write operation Jan 23, 2023 Issued
Array ( [id] => 18409532 [patent_doc_number] => 20230170885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => VOLTAGE CONVERSION CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/157155 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157155
Voltage conversion circuit and memory Jan 19, 2023 Issued
Array ( [id] => 19679062 [patent_doc_number] => 12190933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Refresh address generation circuit [patent_app_type] => utility [patent_app_number] => 18/153312 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 14285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153312
Refresh address generation circuit Jan 10, 2023 Issued
Array ( [id] => 19842524 [patent_doc_number] => 12254923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Nonvolatile SRAM [patent_app_type] => utility [patent_app_number] => 18/149149 [patent_app_country] => US [patent_app_date] => 2023-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149149
Nonvolatile SRAM Jan 1, 2023 Issued
Array ( [id] => 19733562 [patent_doc_number] => 12211562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Data erasure verification for three-dimensional non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/092069 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092069
Data erasure verification for three-dimensional non-volatile memory Dec 29, 2022 Issued
Array ( [id] => 18336021 [patent_doc_number] => 20230127970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MEMORY MODULE MULTIPLE PORT BUFFER TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/087328 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/087328
Memory module multiple port buffer techniques Dec 21, 2022 Issued
Array ( [id] => 18926783 [patent_doc_number] => 20240029787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY CONTROL CIRCUIT PROVIDING DIE-LEVEL READ RETRY TABLE, MEMORY PACKAGE, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/063007 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063007
Memory control circuit providing die-level read retry table, memory package, and storage device Dec 6, 2022 Issued
Array ( [id] => 18438766 [patent_doc_number] => 20230186061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => NON-VOLATILE MEMORIES WITH MIXED OXRAM/FERAM TECHNOLOGIES [patent_app_type] => utility [patent_app_number] => 18/075347 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075347
NON-VOLATILE MEMORIES WITH MIXED OXRAM/FERAM TECHNOLOGIES Dec 4, 2022 Pending
Array ( [id] => 18379416 [patent_doc_number] => 20230154505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/988797 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988797
Page buffer circuit and memory device including the same Nov 16, 2022 Issued
Array ( [id] => 18502341 [patent_doc_number] => 20230225220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/983796 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983796
Magnetic tunneling junction device and memory device including the same Nov 8, 2022 Issued
Array ( [id] => 19811338 [patent_doc_number] => 12242732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Semiconductor apparatus with program operation control [patent_app_type] => utility [patent_app_number] => 17/983115 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983115
Semiconductor apparatus with program operation control Nov 7, 2022 Issued
Array ( [id] => 19828572 [patent_doc_number] => 12249363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Method and apparatus for controlling refresh period of extended memory pool [patent_app_type] => utility [patent_app_number] => 17/980818 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5617 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980818
Method and apparatus for controlling refresh period of extended memory pool Nov 3, 2022 Issued
Array ( [id] => 18194342 [patent_doc_number] => 20230047861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY SYSTEM AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/976566 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976566
Memory system and semiconductor memory device Oct 27, 2022 Issued
Array ( [id] => 19733578 [patent_doc_number] => 12211578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory [patent_app_type] => utility [patent_app_number] => 17/973996 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8014 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973996
DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory Oct 25, 2022 Issued
Array ( [id] => 19567543 [patent_doc_number] => 12142320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/972224 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12228 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/972224
Memory device and method of operating the same Oct 23, 2022 Issued
Menu