
Ming Cheung Po
Examiner (ID: 14994, Phone: (571)270-5552 , Office: P/1771 )
| Most Active Art Unit | 1771 |
| Art Unit(s) | 1797, 1771 |
| Total Applications | 795 |
| Issued Applications | 265 |
| Pending Applications | 99 |
| Abandoned Applications | 459 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19775370
[patent_doc_number] => 20250056796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/519680
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10957
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519680
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/519680 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE MEMORY DEVICE | Nov 26, 2023 | Pending |
Array
(
[id] => 19175849
[patent_doc_number] => 20240161823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => MEMORY DEVICE BASED ON PHASE CHANGE MEMORY FOR DEEP NEURAL NETWORK AND METHOD FOR STORING WEIGHT THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/508745
[patent_app_country] => US
[patent_app_date] => 2023-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10050
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508745
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/508745 | MEMORY DEVICE BASED ON PHASE CHANGE MEMORY FOR DEEP NEURAL NETWORK AND METHOD FOR STORING WEIGHT THEREOF | Nov 13, 2023 | Pending |
Array
(
[id] => 20162949
[patent_doc_number] => 12389606
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => MRAM structure and fabricating method of the same
[patent_app_type] => utility
[patent_app_number] => 18/508204
[patent_app_country] => US
[patent_app_date] => 2023-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/508204 | MRAM structure and fabricating method of the same | Nov 12, 2023 | Issued |
Array
(
[id] => 19783281
[patent_doc_number] => 12232336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/506157
[patent_app_country] => US
[patent_app_date] => 2023-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 60
[patent_no_of_words] => 12314
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18506157
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/506157 | Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same | Nov 9, 2023 | Issued |
Array
(
[id] => 19175850
[patent_doc_number] => 20240161824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/503719
[patent_app_country] => US
[patent_app_date] => 2023-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503719
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/503719 | MEMORY DEVICE AND OPERATING METHOD OF THEREOF | Nov 6, 2023 | Pending |
Array
(
[id] => 20636586
[patent_doc_number] => 12597467
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Adaptive memory management and control circuitry
[patent_app_type] => utility
[patent_app_number] => 18/501597
[patent_app_country] => US
[patent_app_date] => 2023-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501597
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/501597 | Adaptive memory management and control circuitry | Nov 2, 2023 | Issued |
Array
(
[id] => 19205873
[patent_doc_number] => 20240177772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => MEMORY DEVICE PERFORMING MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 18/494652
[patent_app_country] => US
[patent_app_date] => 2023-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17526
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494652
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/494652 | Memory device performing multiplication using logical states of memory cells | Oct 24, 2023 | Issued |
Array
(
[id] => 18926761
[patent_doc_number] => 20240029765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => Methods for Programming and Accessing Resistive Change Elements Using Neutral Voltage Conditions
[patent_app_type] => utility
[patent_app_number] => 18/375968
[patent_app_country] => US
[patent_app_date] => 2023-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 113917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375968
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/375968 | Methods for Programming and Accessing Resistive Change Elements Using Neutral Voltage Conditions | Oct 1, 2023 | Abandoned |
Array
(
[id] => 19100775
[patent_doc_number] => 20240120003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => DEVICES AND METHODS FOR READING A MEMRISTIVE ELEMENT
[patent_app_type] => utility
[patent_app_number] => 18/374689
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 32041
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374689
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/374689 | DEVICES AND METHODS FOR READING A MEMRISTIVE ELEMENT | Sep 28, 2023 | Pending |
Array
(
[id] => 19100777
[patent_doc_number] => 20240120005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => DEVICES AND METHODS FOR OPERATING A MEMRISTIVE ELEMENT
[patent_app_type] => utility
[patent_app_number] => 18/374693
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 40349
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374693
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/374693 | Devices and methods for operating a memristive element | Sep 28, 2023 | Issued |
Array
(
[id] => 19116138
[patent_doc_number] => 20240127888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SYSTEM AND METHOD FOR ADDITION AND SUBTRACTION IN MEMRISTOR-BASED IN-MEMORY COMPUTING
[patent_app_type] => utility
[patent_app_number] => 18/476499
[patent_app_country] => US
[patent_app_date] => 2023-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5625
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476499
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/476499 | SYSTEM AND METHOD FOR ADDITION AND SUBTRACTION IN MEMRISTOR-BASED IN-MEMORY COMPUTING | Sep 27, 2023 | Pending |
Array
(
[id] => 18898343
[patent_doc_number] => 20240013828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => MEMORY DEVICE HAVING BITLINE SEGMENTED INTO BITLINE SEGMENTS AND RELATED METHOD FOR OPERATING MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/472282
[patent_app_country] => US
[patent_app_date] => 2023-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12143
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472282
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/472282 | Memory device having bitline segmented into bitline segments and related method for operating memory device | Sep 21, 2023 | Issued |
Array
(
[id] => 18865622
[patent_doc_number] => 20230420059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => Data Storage Device and Method for Predicting Future Read Thresholds
[patent_app_type] => utility
[patent_app_number] => 18/242061
[patent_app_country] => US
[patent_app_date] => 2023-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242061
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/242061 | Data storage device and method for predicting future read thresholds | Sep 4, 2023 | Issued |
Array
(
[id] => 19803730
[patent_doc_number] => 20250069655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => BIT-SERIAL INPUT SCHEMES FOR CROSSBAR CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/456452
[patent_app_country] => US
[patent_app_date] => 2023-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6580
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456452
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/456452 | BIT-SERIAL INPUT SCHEMES FOR CROSSBAR CIRCUITS | Aug 24, 2023 | Pending |
Array
(
[id] => 19803733
[patent_doc_number] => 20250069658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => Threshold Voltage Reduction in Memristive Devices
[patent_app_type] => utility
[patent_app_number] => 18/237787
[patent_app_country] => US
[patent_app_date] => 2023-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8482
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237787
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/237787 | Threshold Voltage Reduction in Memristive Devices | Aug 23, 2023 | Pending |
Array
(
[id] => 18820810
[patent_doc_number] => 20230395151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => INTERLEAVED STRING DRIVERS, STRING DRIVER WITH NARROW ACTIVE REGION, AND GATED LDD STRING DRIVER
[patent_app_type] => utility
[patent_app_number] => 18/237070
[patent_app_country] => US
[patent_app_date] => 2023-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9851
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237070
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/237070 | Interleaved string drivers, string driver with narrow active region, and gated LDD string driver | Aug 22, 2023 | Issued |
Array
(
[id] => 19626884
[patent_doc_number] => 12165731
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 18/447910
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 29
[patent_no_of_words] => 21842
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447910
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447910 | Memory device | Aug 9, 2023 | Issued |
Array
(
[id] => 19604450
[patent_doc_number] => 20240395330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => ENABLING SIGNIFICANT SCALING OF WORDLINE SWITCH WITH WORDLINE DEPENDENT NEGATIVE BITLINE VOLTAGE
[patent_app_type] => utility
[patent_app_number] => 18/230078
[patent_app_country] => US
[patent_app_date] => 2023-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17044
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230078
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/230078 | Enabling significant scaling of wordline switch with wordline dependent negative bitline voltage | Aug 2, 2023 | Issued |
Array
(
[id] => 19459944
[patent_doc_number] => 12100445
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Integrated circuit and method
[patent_app_type] => utility
[patent_app_number] => 18/362393
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 10963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362393
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362393 | Integrated circuit and method | Jul 30, 2023 | Issued |
Array
(
[id] => 19749200
[patent_doc_number] => 20250037765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => SUPPRESSING RANDOM TELEGRAPH NOISE IN CROSSBAR CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/361282
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361282
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361282 | Suppressing random telegraph noise in crossbar circuits | Jul 27, 2023 | Issued |