Search

Ming Y. Hon

Examiner (ID: 12806, Phone: (571)270-5245 , Office: P/2675 )

Most Active Art Unit
2666
Art Unit(s)
2625, 2666, 2675
Total Applications
838
Issued Applications
670
Pending Applications
56
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20404449 [patent_doc_number] => 12494430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Integrated circuit devices including lower interconnect metal layers at cell boundaries and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/752851 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 4555 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752851
Integrated circuit devices including lower interconnect metal layers at cell boundaries and methods of forming the same Jun 24, 2024 Issued
Array ( [id] => 19452668 [patent_doc_number] => 20240312798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/675560 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675560
Semiconductor die package with ring structure May 27, 2024 Issued
Array ( [id] => 19452798 [patent_doc_number] => 20240312928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/673099 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673099
Method of forming a region shielding within a package of a microelectronic device May 22, 2024 Issued
Array ( [id] => 19468152 [patent_doc_number] => 20240321822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING [patent_app_type] => utility [patent_app_number] => 18/668777 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668777
Semiconductor assemblies with redistribution structures for die stack signal routing May 19, 2024 Issued
Array ( [id] => 19733927 [patent_doc_number] => 12211929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-28 [patent_title] => Heterojunction bipolar transistors with terminals having a non-planar arrangement [patent_app_type] => utility [patent_app_number] => 18/663523 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663523
Heterojunction bipolar transistors with terminals having a non-planar arrangement May 13, 2024 Issued
Array ( [id] => 19918576 [patent_doc_number] => 12293952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Electronic package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/659692 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 1057 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659692
Electronic package and manufacturing method thereof May 8, 2024 Issued
Array ( [id] => 19407163 [patent_doc_number] => 20240290674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/655822 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655822
Electronic package comprising conductive layer connected electrode pad through electronic component May 5, 2024 Issued
Array ( [id] => 19421016 [patent_doc_number] => 20240297140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => INTEGRATED CIRCUIT PACKAGES HAVING ADHESION LAYERS FOR THROUGH VIAS [patent_app_type] => utility [patent_app_number] => 18/656277 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656277
Integrated circuit packages having adhesion layers for through vias May 5, 2024 Issued
Array ( [id] => 19422371 [patent_doc_number] => 20240298495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => DISPLAY PANEL HAVING AN ARRANGEMENT BY UNIT PIXEL PAIRS [patent_app_type] => utility [patent_app_number] => 18/646520 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646520
DISPLAY PANEL HAVING AN ARRANGEMENT BY UNIT PIXEL PAIRS Apr 24, 2024 Pending
Array ( [id] => 19384800 [patent_doc_number] => 20240274670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/642509 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642509
Semiconductor device Apr 21, 2024 Issued
Array ( [id] => 19364265 [patent_doc_number] => 20240266299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE STRUCTURE AND SHIELDING LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/640476 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640476
Semiconductor devices comprising interconnect terminal with concave recess exposed from dielectric structure at lateral and bottom side of the substrate and methods of manufacturing semiconductor devices Apr 18, 2024 Issued
Array ( [id] => 19349282 [patent_doc_number] => 20240258246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Semiconductor Device with Compartment Shield Formed from Metal Bars and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 18/635819 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635819
Semiconductor device with compartment shield formed from metal bars and manufacturing method thereof Apr 14, 2024 Issued
Array ( [id] => 19392993 [patent_doc_number] => 20240282863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => THIN-FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/634854 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634854
Thin-film transistor and display device including the same Apr 11, 2024 Issued
Array ( [id] => 19349265 [patent_doc_number] => 20240258229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE INCLUDING MULTIPLE SUBSTRATES WITH DIFFERENT FUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/631020 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631020
SEMICONDUCTOR DEVICE PACKAGE INCLUDING MULTIPLE SUBSTRATES WITH DIFFERENT FUNCTIONS Apr 8, 2024 Issued
Array ( [id] => 19351410 [patent_doc_number] => 20240260374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/622759 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -47 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622759
DISPLAY APPARATUS Mar 28, 2024 Pending
Array ( [id] => 19765954 [patent_doc_number] => 12224255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Electronic package including lead frame having multiple conductive posts [patent_app_type] => utility [patent_app_number] => 18/607815 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4737 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607815
Electronic package including lead frame having multiple conductive posts Mar 17, 2024 Issued
Array ( [id] => 19285840 [patent_doc_number] => 20240222317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING AIR CAVITY [patent_app_type] => utility [patent_app_number] => 18/604804 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604804
Method of manufacturing semiconductor device having air cavity Mar 13, 2024 Issued
Array ( [id] => 20435036 [patent_doc_number] => 12506087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Semiconductor package with redistribution structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/603174 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 9597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603174
Semiconductor package with redistribution structure and manufacturing method thereof Mar 11, 2024 Issued
Array ( [id] => 19335751 [patent_doc_number] => 20240250181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/595629 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595629
Semiconductor device comprising conductive layers functioning as first and second gate electrodes of a transistor Mar 4, 2024 Issued
Array ( [id] => 19943654 [patent_doc_number] => 12315790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Compact routing package for high frequency isolation [patent_app_type] => utility [patent_app_number] => 18/596303 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596303
Compact routing package for high frequency isolation Mar 4, 2024 Issued
Menu