Search

Ming Y. Hon

Examiner (ID: 12806, Phone: (571)270-5245 , Office: P/2675 )

Most Active Art Unit
2666
Art Unit(s)
2625, 2666, 2675
Total Applications
838
Issued Applications
670
Pending Applications
56
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20163091 [patent_doc_number] => 12389750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Display panel, display device, and method for preparing display panel [patent_app_type] => utility [patent_app_number] => 17/799385 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/799385
Display panel, display device, and method for preparing display panel Oct 21, 2021 Issued
Array ( [id] => 18320583 [patent_doc_number] => 20230118711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => PACKAGE DEVICE, MEMORY DEVICE, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/450835 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450835
Package device comprising electrostatic discharge protection element Oct 13, 2021 Issued
Array ( [id] => 19030068 [patent_doc_number] => 11929437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor device comprising various thin-film transistors [patent_app_type] => utility [patent_app_number] => 17/500020 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 34 [patent_no_of_words] => 20513 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500020
Semiconductor device comprising various thin-film transistors Oct 12, 2021 Issued
Array ( [id] => 17402922 [patent_doc_number] => 20220045013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MODULE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/497177 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497177
Package module comprising shield film on semiconductor device and method of manufacturing the same Oct 7, 2021 Issued
Array ( [id] => 17373747 [patent_doc_number] => 20220028799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MODULE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/497132 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497132
Package module comprising marking and shield films and method of manufacturing the same Oct 7, 2021 Issued
Array ( [id] => 18088593 [patent_doc_number] => 11538732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for forming board assembly with chemical vapor deposition diamond (CVDD) windows for thermal transport [patent_app_type] => utility [patent_app_number] => 17/493476 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493476
Method for forming board assembly with chemical vapor deposition diamond (CVDD) windows for thermal transport Oct 3, 2021 Issued
Array ( [id] => 19873753 [patent_doc_number] => 12266624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Semiconductor die with solder restraining wall [patent_app_type] => utility [patent_app_number] => 17/488715 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5052 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488715
Semiconductor die with solder restraining wall Sep 28, 2021 Issued
Array ( [id] => 19460142 [patent_doc_number] => 12100649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Package comprising an integrated device with a back side metal layer [patent_app_type] => utility [patent_app_number] => 17/482294 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10191 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482294
Package comprising an integrated device with a back side metal layer Sep 21, 2021 Issued
Array ( [id] => 17477382 [patent_doc_number] => 20220084886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/447468 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447468
WAFER PROCESSING METHOD Sep 12, 2021 Abandoned
Array ( [id] => 18540890 [patent_doc_number] => 20230246001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/009920 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18009920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/009920
SEMICONDUCTOR DEVICE Sep 8, 2021 Pending
Array ( [id] => 20390861 [patent_doc_number] => 12490612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Display substrate comprising signal lines and signal access pins and display apparatus [patent_app_type] => utility [patent_app_number] => 17/796256 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13549 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796256
Display substrate comprising signal lines and signal access pins and display apparatus Sep 8, 2021 Issued
Array ( [id] => 17463769 [patent_doc_number] => 20220077075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => PANEL LEVEL METAL WALL GRIDS ARRAY FOR INTEGRATED CIRCUIT PACKAGING AND ASSOCIATED MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/469822 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469822
Panel level metal wall grids array for integrated circuit packaging Sep 7, 2021 Issued
Array ( [id] => 18227758 [patent_doc_number] => 20230066752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/462505 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462505
Semiconductor die package with ring structure for controlling warpage of a package substrate Aug 30, 2021 Issued
Array ( [id] => 18226081 [patent_doc_number] => 20230065075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WAFER CHIP SCALE PACKAGES WITH VISIBLE SOLDER FILLETS [patent_app_type] => utility [patent_app_number] => 17/463047 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463047 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463047
Wafer chip scale packages with visible solder fillets Aug 30, 2021 Issued
Array ( [id] => 19294599 [patent_doc_number] => 12033963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Package structure comprising thermally conductive layer around the IC die [patent_app_type] => utility [patent_app_number] => 17/461957 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461957
Package structure comprising thermally conductive layer around the IC die Aug 29, 2021 Issued
Array ( [id] => 18767002 [patent_doc_number] => 11817413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor package structure comprising via structure and redistribution layer structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/460647 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460647
Semiconductor package structure comprising via structure and redistribution layer structure and method for forming the same Aug 29, 2021 Issued
Array ( [id] => 18343444 [patent_doc_number] => 11640928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Heat dispersion layers for double sided interconnect [patent_app_type] => utility [patent_app_number] => 17/412423 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412423
Heat dispersion layers for double sided interconnect Aug 25, 2021 Issued
Array ( [id] => 18840155 [patent_doc_number] => 11848234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Semiconductor package and method comprising formation of redistribution structure and interconnecting die [patent_app_type] => utility [patent_app_number] => 17/412625 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 9790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412625
Semiconductor package and method comprising formation of redistribution structure and interconnecting die Aug 25, 2021 Issued
Array ( [id] => 17278044 [patent_doc_number] => 20210384242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => METAL MIRROR BASED MULTISPECTRAL FILTER ARRAY [patent_app_type] => utility [patent_app_number] => 17/445623 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445623
Metal mirror based multispectral filter array Aug 22, 2021 Issued
Array ( [id] => 18210317 [patent_doc_number] => 20230056579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => APPARATUS INCLUDING INTEGRATED PADS AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/408343 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408343
Apparatus including integrated pads and methods of manufacturing the same Aug 19, 2021 Issued
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