
Ming Y. Hon
Examiner (ID: 12806, Phone: (571)270-5245 , Office: P/2675 )
| Most Active Art Unit | 2666 |
| Art Unit(s) | 2625, 2666, 2675 |
| Total Applications | 838 |
| Issued Applications | 670 |
| Pending Applications | 56 |
| Abandoned Applications | 135 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18456351
[patent_doc_number] => 20230197633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND SHIELDING HOUSING OF SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/173080
[patent_app_country] => US
[patent_app_date] => 2023-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7807
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173080
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/173080 | Semiconductor package, semiconductor device and shielding housing of semiconductor package | Feb 22, 2023 | Issued |
Array
(
[id] => 19610932
[patent_doc_number] => 12159813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-03
[patent_title] => Embedded bridge die with through-silicon vias
[patent_app_type] => utility
[patent_app_number] => 18/111329
[patent_app_country] => US
[patent_app_date] => 2023-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 45
[patent_no_of_words] => 13144
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111329
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/111329 | Embedded bridge die with through-silicon vias | Feb 16, 2023 | Issued |
Array
(
[id] => 18473221
[patent_doc_number] => 20230207509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => MULTI-LAYER SEMICONDUCTOR PACKAGE WITH STACKED PASSIVE COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 18/171028
[patent_app_country] => US
[patent_app_date] => 2023-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4782
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171028
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/171028 | Multi-layer semiconductor package with stacked passive components | Feb 16, 2023 | Issued |
Array
(
[id] => 19364308
[patent_doc_number] => 20240266342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => COLUMN DIVIDED MULTI-HEIGHT ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 18/165259
[patent_app_country] => US
[patent_app_date] => 2023-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165259
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/165259 | COLUMN DIVIDED MULTI-HEIGHT ARCHITECTURE | Feb 5, 2023 | Pending |
Array
(
[id] => 19023191
[patent_doc_number] => 20240079362
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/104789
[patent_app_country] => US
[patent_app_date] => 2023-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9128
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104789
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/104789 | SEMICONDUCTOR DEVICE | Feb 1, 2023 | Pending |
Array
(
[id] => 18540875
[patent_doc_number] => 20230245986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/103196
[patent_app_country] => US
[patent_app_date] => 2023-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103196
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/103196 | Multiple conductive posts | Jan 29, 2023 | Issued |
Array
(
[id] => 18408958
[patent_doc_number] => 20230170311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => Laser-Based Redistribution and Multi-Stacked Packages
[patent_app_type] => utility
[patent_app_number] => 18/161693
[patent_app_country] => US
[patent_app_date] => 2023-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161693
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/161693 | Laser-based redistribution and multi-stacked packages | Jan 29, 2023 | Issued |
Array
(
[id] => 19093974
[patent_doc_number] => 11955439
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Semiconductor package with redistribution structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/155672
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 36
[patent_no_of_words] => 14706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155672
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155672 | Semiconductor package with redistribution structure and manufacturing method thereof | Jan 16, 2023 | Issued |
Array
(
[id] => 19321451
[patent_doc_number] => 20240242998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => MICRO-DEVICE SUBSTRATE STRUCTURES WITH POSTS AND INDENTATIONS
[patent_app_type] => utility
[patent_app_number] => 18/098066
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098066
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/098066 | MICRO-DEVICE SUBSTRATE STRUCTURES WITH POSTS AND INDENTATIONS | Jan 16, 2023 | Pending |
Array
(
[id] => 20175907
[patent_doc_number] => 12394662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => Method for patterning active areas comprising different operations in semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 18/097336
[patent_app_country] => US
[patent_app_date] => 2023-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 58
[patent_no_of_words] => 5539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097336
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097336 | Method for patterning active areas comprising different operations in semiconductor structure | Jan 15, 2023 | Issued |
Array
(
[id] => 19842772
[patent_doc_number] => 12255172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine
[patent_app_type] => utility
[patent_app_number] => 18/096179
[patent_app_country] => US
[patent_app_date] => 2023-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 4617
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096179
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/096179 | Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine | Jan 11, 2023 | Issued |
Array
(
[id] => 19321527
[patent_doc_number] => 20240243074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => COAXIAL I/O DIE
[patent_app_type] => utility
[patent_app_number] => 18/153470
[patent_app_country] => US
[patent_app_date] => 2023-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 30325
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153470
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/153470 | COAXIAL I/O DIE | Jan 11, 2023 | Pending |
Array
(
[id] => 18409060
[patent_doc_number] => 20230170413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/095641
[patent_app_country] => US
[patent_app_date] => 2023-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6143
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/095641 | Semiconductor device comprising separate different well regions with doping types | Jan 10, 2023 | Issued |
Array
(
[id] => 19285862
[patent_doc_number] => 20240222339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => Integrated Circuit Package With Improved Heat Dissipation Efficiency and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/152665
[patent_app_country] => US
[patent_app_date] => 2023-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152665
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/152665 | Integrated Circuit Package With Improved Heat Dissipation Efficiency and Methods of Forming the Same | Jan 9, 2023 | Pending |
Array
(
[id] => 19007963
[patent_doc_number] => 20240072034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => 3DIC Package and Method Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/151609
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151609
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/151609 | 3DIC Package and Method Forming the Same | Jan 8, 2023 | Pending |
Array
(
[id] => 18363882
[patent_doc_number] => 20230145473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING
[patent_app_type] => utility
[patent_app_number] => 18/094320
[patent_app_country] => US
[patent_app_date] => 2023-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6582
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094320
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094320 | Semiconductor assemblies with redistribution structures for die stack signal routing | Jan 5, 2023 | Issued |
Array
(
[id] => 18379778
[patent_doc_number] => 20230154867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => CHIP STRUCTURE AND SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/150866
[patent_app_country] => US
[patent_app_date] => 2023-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6922
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150866
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/150866 | Chip structure and semiconductor structure comprising auxiliary bonding region above guard ring structure | Jan 5, 2023 | Issued |
Array
(
[id] => 18361790
[patent_doc_number] => 20230143381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/150541
[patent_app_country] => US
[patent_app_date] => 2023-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4487
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150541
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/150541 | Electronic device comprising a transferred portion of plurality of chips and method for manufacturing the same | Jan 4, 2023 | Issued |
Array
(
[id] => 18347938
[patent_doc_number] => 20230136049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/092922
[patent_app_country] => US
[patent_app_date] => 2023-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092922
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/092922 | Semiconductor device package including multiple substrates with different functions | Jan 2, 2023 | Issued |
Array
(
[id] => 19023173
[patent_doc_number] => 20240079344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => PACKAGING ASSEMBLY FOR SEMICONDUCTOR DEVICE AND METHOD OF MAKING
[patent_app_type] => utility
[patent_app_number] => 18/092852
[patent_app_country] => US
[patent_app_date] => 2023-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092852
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/092852 | PACKAGING ASSEMBLY FOR SEMICONDUCTOR DEVICE AND METHOD OF MAKING | Jan 2, 2023 | Abandoned |