Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20010862 [patent_doc_number] => 20250149084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND METHOD OF IMPLEMENTING MULTI-LEVEL MEMORY BY USING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/785752 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785752
MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND METHOD OF IMPLEMENTING MULTI-LEVEL MEMORY BY USING THE MEMORY DEVICE Jul 25, 2024 Pending
Array ( [id] => 19866010 [patent_doc_number] => 20250104796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => PERFORMING CORRECTIVE SENSE OPERATIONS IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/786016 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786016
PERFORMING CORRECTIVE SENSE OPERATIONS IN MEMORY Jul 25, 2024 Pending
Array ( [id] => 19574873 [patent_doc_number] => 20240379165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/781505 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781505
MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE Jul 22, 2024 Pending
Array ( [id] => 20273485 [patent_doc_number] => 12443265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/754190 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3416 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754190
Storage device and operating method thereof Jun 25, 2024 Issued
Array ( [id] => 20429363 [patent_doc_number] => 20250391456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => STEP VOLTAGE DURING CURRENT FORCE READ OF PROGRAMMABLE RESISTANCE MEMORY CELL WITH THRESHOLD SWITCHING SELECTOR [patent_app_type] => utility [patent_app_number] => 18/749289 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749289
STEP VOLTAGE DURING CURRENT FORCE READ OF PROGRAMMABLE RESISTANCE MEMORY CELL WITH THRESHOLD SWITCHING SELECTOR Jun 19, 2024 Pending
Array ( [id] => 19483736 [patent_doc_number] => 20240331778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/744146 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744146
Managing compensation for charge coupling and lateral migration in memory devices Jun 13, 2024 Issued
Array ( [id] => 19467684 [patent_doc_number] => 20240321354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/735782 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735782
Memory device and operating method thereof Jun 5, 2024 Issued
Array ( [id] => 19771876 [patent_doc_number] => 20250053302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/671484 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671484
MEMORY DEVICE May 21, 2024 Pending
Array ( [id] => 20359935 [patent_doc_number] => 12475939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Pre-decoder circuitry [patent_app_type] => utility [patent_app_number] => 18/667802 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5696 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667802
Pre-decoder circuitry May 16, 2024 Issued
Array ( [id] => 20096101 [patent_doc_number] => 20250226037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => MEMORY DEVICES AND OPERATION METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/666520 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666520
MEMORY DEVICES AND OPERATION METHODS THEREOF, AND MEMORY SYSTEMS May 15, 2024 Pending
Array ( [id] => 19589367 [patent_doc_number] => 20240386924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME [patent_app_type] => utility [patent_app_number] => 18/658864 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658864
Apparatuses including multiple read modes and methods for same May 7, 2024 Issued
Array ( [id] => 19406871 [patent_doc_number] => 20240290382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/658819 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658819
Semiconductor memory device May 7, 2024 Issued
Array ( [id] => 19850410 [patent_doc_number] => 20250095761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => HIGH VOLTAGE TRANSFER DEVICE AND A MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/636542 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636542
HIGH VOLTAGE TRANSFER DEVICE AND A MEMORY DEVICE INCLUDING THE SAME Apr 15, 2024 Pending
Array ( [id] => 19335331 [patent_doc_number] => 20240249761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => POWER SUPPLY GENERATOR ASSIST [patent_app_type] => utility [patent_app_number] => 18/626718 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626718
POWER SUPPLY GENERATOR ASSIST Apr 3, 2024 Pending
Array ( [id] => 20250895 [patent_doc_number] => 20250299764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR SIGNAL REDUNDANCY IN STACKED-CHIP ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/611580 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611580
APPARATUSES, SYSTEMS, AND METHODS FOR SIGNAL REDUNDANCY IN STACKED-CHIP ARCHITECTURES Mar 19, 2024 Pending
Array ( [id] => 20044614 [patent_doc_number] => 20250182836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => COMPUTE-IN-MEMORY ARRAY MULTI-RANGE TEMPERATURE COMPENSATION [patent_app_type] => utility [patent_app_number] => 18/594660 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594660
COMPUTE-IN-MEMORY ARRAY MULTI-RANGE TEMPERATURE COMPENSATION Mar 3, 2024 Pending
Array ( [id] => 19335340 [patent_doc_number] => 20240249770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Superconductive Memory Cells and Devices [patent_app_type] => utility [patent_app_number] => 18/587872 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587872
Superconductive memory cells and devices Feb 25, 2024 Issued
Array ( [id] => 20019276 [patent_doc_number] => 20250157498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE FOR DRIVING AN INTERNAL VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/437481 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437481
VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE FOR DRIVING AN INTERNAL VOLTAGE Feb 8, 2024 Pending
Array ( [id] => 19467711 [patent_doc_number] => 20240321381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/420867 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420867
MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF Jan 23, 2024 Pending
Array ( [id] => 19835473 [patent_doc_number] => 20250087259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => MEMORY CIRCUIT, INTERFACE CIRCUIT FOR MEMORY CIRCUIT, AND METHOD OF OPERATING MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/421138 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421138
MEMORY CIRCUIT, INTERFACE CIRCUIT FOR MEMORY CIRCUIT, AND METHOD OF OPERATING MEMORY CIRCUIT Jan 23, 2024 Pending
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