Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17010642 [patent_doc_number] => 20210241803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => MEMORY DEVICE AND POWER MANAGEMENT METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/031925 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031925
Memory device and power management method using the same Sep 24, 2020 Issued
Array ( [id] => 16560122 [patent_doc_number] => 20210005271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/029265 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029265
Non-volatile memory device, operating method thereof, and storage device having the same Sep 22, 2020 Issued
Array ( [id] => 17485650 [patent_doc_number] => 20220093154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => WRITE DRIVER BOOST CIRCUIT FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/024759 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024759
Write driver boost circuit for memory cells Sep 17, 2020 Issued
Array ( [id] => 17772173 [patent_doc_number] => 11404124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Voltage bin boundary calibration at memory device power up [patent_app_type] => utility [patent_app_number] => 17/022908 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022908
Voltage bin boundary calibration at memory device power up Sep 15, 2020 Issued
Array ( [id] => 17862616 [patent_doc_number] => 11443777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Backside power rail architecture [patent_app_type] => utility [patent_app_number] => 17/019030 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019030
Backside power rail architecture Sep 10, 2020 Issued
Array ( [id] => 18131142 [patent_doc_number] => 11557357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Selection of read offset values in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/014583 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014583
Selection of read offset values in a memory sub-system Sep 7, 2020 Issued
Array ( [id] => 17716404 [patent_doc_number] => 11380402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/011555 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011555
Memory system and operating method thereof Sep 2, 2020 Issued
Array ( [id] => 16723519 [patent_doc_number] => 20210090666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/008209 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008209
Semiconductor memory device Aug 30, 2020 Issued
Array ( [id] => 17825540 [patent_doc_number] => 11430492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Apparatuses including multiple read modes and methods for same [patent_app_type] => utility [patent_app_number] => 17/006029 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7457 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006029
Apparatuses including multiple read modes and methods for same Aug 27, 2020 Issued
Array ( [id] => 17447853 [patent_doc_number] => 20220068358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SYSTEMS AND METHODS FOR LEVEL DOWN SHIFTING DRIVERS [patent_app_type] => utility [patent_app_number] => 17/006097 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006097
Systems and methods for level down shifting drivers Aug 27, 2020 Issued
Array ( [id] => 17447856 [patent_doc_number] => 20220068361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUSES AND METHODS FOR CONTROL OF REFRESH OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/004235 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004235
Apparatuses and methods for control of refresh operations Aug 26, 2020 Issued
Array ( [id] => 16515812 [patent_doc_number] => 20200395070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/003761 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003761
Resistive random access memory device Aug 25, 2020 Issued
Array ( [id] => 17908423 [patent_doc_number] => 11462283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods [patent_app_type] => utility [patent_app_number] => 17/003363 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003363
Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods Aug 25, 2020 Issued
Array ( [id] => 17606920 [patent_doc_number] => 11335412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Managing sub-block erase operations in a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/991836 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991836
Managing sub-block erase operations in a memory sub-system Aug 11, 2020 Issued
Array ( [id] => 16471424 [patent_doc_number] => 20200372962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DYNAMIC PROGRAMMING OF VALLEY MARGINS [patent_app_type] => utility [patent_app_number] => 16/990859 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990859
Dynamic programming of valley margins Aug 10, 2020 Issued
Array ( [id] => 17326260 [patent_doc_number] => 11217285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-04 [patent_title] => Memory subsystem calibration using substitute results [patent_app_type] => utility [patent_app_number] => 16/986116 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/986116
Memory subsystem calibration using substitute results Aug 4, 2020 Issued
Array ( [id] => 17130038 [patent_doc_number] => 20210304807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => ERROR CORRECTION METHODS AND SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/943788 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943788
Error correction methods and semiconductor devices and semiconductor systems using the same Jul 29, 2020 Issued
Array ( [id] => 16515800 [patent_doc_number] => 20200395058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SELF REFERENCE FOR FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/921860 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921860
Self reference for ferroelectric memory Jul 5, 2020 Issued
Array ( [id] => 17637917 [patent_doc_number] => 11348646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Apparatus and method for managing program operation time and write latency in memory system [patent_app_type] => utility [patent_app_number] => 16/920165 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 17349 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920165
Apparatus and method for managing program operation time and write latency in memory system Jul 1, 2020 Issued
Array ( [id] => 17543910 [patent_doc_number] => 11309042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise [patent_app_type] => utility [patent_app_number] => 16/915289 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915289 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915289
Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise Jun 28, 2020 Issued
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