Search

Minh D. Dinh

Examiner (ID: 2733, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
488
Issued Applications
449
Pending Applications
33
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18120332 [patent_doc_number] => 11551730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Low power memory system using dual input-output voltage supplies [patent_app_type] => utility [patent_app_number] => 17/158485 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11393 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158485
Low power memory system using dual input-output voltage supplies Jan 25, 2021 Issued
Array ( [id] => 18046535 [patent_doc_number] => 11520489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/148161 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148161
Memory device and method of operating the same Jan 12, 2021 Issued
Array ( [id] => 19022871 [patent_doc_number] => 20240079042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => COUNTER-BASED SELECTIVE ROW HAMMER REFRESH APPARATUS AND METHOD FOR ROW HAMMER PREVENTION [patent_app_type] => utility [patent_app_number] => 18/268651 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18268651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/268651
Counter-based selective row hammer refresh apparatus and method for row hammer prevention Jan 10, 2021 Issued
Array ( [id] => 18464141 [patent_doc_number] => 11688434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Internal voltage generation circuit and semiconductor memory apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/144543 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144543
Internal voltage generation circuit and semiconductor memory apparatus including the same Jan 7, 2021 Issued
Array ( [id] => 18073530 [patent_doc_number] => 11532367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Managing programming convergence associated with memory cells of a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/115357 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115357
Managing programming convergence associated with memory cells of a memory sub-system Dec 7, 2020 Issued
Array ( [id] => 17224477 [patent_doc_number] => 11176987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Dram array architecture with row hammer stress mitigation [patent_app_type] => utility [patent_app_number] => 17/114404 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114404
Dram array architecture with row hammer stress mitigation Dec 6, 2020 Issued
Array ( [id] => 17522309 [patent_doc_number] => 20220108158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => ULTRALOW POWER INFERENCE ENGINE WITH EXTERNAL MAGNETIC FIELD PROGRAMMING ASSISTANCE [patent_app_type] => utility [patent_app_number] => 17/061798 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061798 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061798
Ultralow power inference engine with external magnetic field programming assistance Oct 1, 2020 Issued
Array ( [id] => 17253857 [patent_doc_number] => 11189353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Memory system and memory control method [patent_app_type] => utility [patent_app_number] => 17/060767 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6008 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060767
Memory system and memory control method Sep 30, 2020 Issued
Array ( [id] => 17010642 [patent_doc_number] => 20210241803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => MEMORY DEVICE AND POWER MANAGEMENT METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/031925 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031925
Memory device and power management method using the same Sep 24, 2020 Issued
Array ( [id] => 16560122 [patent_doc_number] => 20210005271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/029265 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029265
Non-volatile memory device, operating method thereof, and storage device having the same Sep 22, 2020 Issued
Array ( [id] => 17485650 [patent_doc_number] => 20220093154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => WRITE DRIVER BOOST CIRCUIT FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/024759 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024759
Write driver boost circuit for memory cells Sep 17, 2020 Issued
Array ( [id] => 17772173 [patent_doc_number] => 11404124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Voltage bin boundary calibration at memory device power up [patent_app_type] => utility [patent_app_number] => 17/022908 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022908
Voltage bin boundary calibration at memory device power up Sep 15, 2020 Issued
Array ( [id] => 17862616 [patent_doc_number] => 11443777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Backside power rail architecture [patent_app_type] => utility [patent_app_number] => 17/019030 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019030
Backside power rail architecture Sep 10, 2020 Issued
Array ( [id] => 18131142 [patent_doc_number] => 11557357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Selection of read offset values in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/014583 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014583
Selection of read offset values in a memory sub-system Sep 7, 2020 Issued
Array ( [id] => 17716404 [patent_doc_number] => 11380402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/011555 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011555
Memory system and operating method thereof Sep 2, 2020 Issued
Array ( [id] => 16723519 [patent_doc_number] => 20210090666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/008209 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008209
Semiconductor memory device Aug 30, 2020 Issued
Array ( [id] => 17447853 [patent_doc_number] => 20220068358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SYSTEMS AND METHODS FOR LEVEL DOWN SHIFTING DRIVERS [patent_app_type] => utility [patent_app_number] => 17/006097 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006097
Systems and methods for level down shifting drivers Aug 27, 2020 Issued
Array ( [id] => 17825540 [patent_doc_number] => 11430492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Apparatuses including multiple read modes and methods for same [patent_app_type] => utility [patent_app_number] => 17/006029 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7457 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006029
Apparatuses including multiple read modes and methods for same Aug 27, 2020 Issued
Array ( [id] => 17447856 [patent_doc_number] => 20220068361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUSES AND METHODS FOR CONTROL OF REFRESH OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/004235 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004235
Apparatuses and methods for control of refresh operations Aug 26, 2020 Issued
Array ( [id] => 16515812 [patent_doc_number] => 20200395070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/003761 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003761
Resistive random access memory device Aug 25, 2020 Issued
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