Minh D. Dinh

Array ( [id] => 16471424 [patent_doc_number] => 20200372962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DYNAMIC PROGRAMMING OF VALLEY MARGINS [patent_app_type] => utility [patent_app_number] => 16/990859 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17326260 [patent_doc_number] => 11217285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-04 [patent_title] => Memory subsystem calibration using substitute results [patent_app_type] => utility [patent_app_number] => 16/986116 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17130038 [patent_doc_number] => 20210304807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => ERROR CORRECTION METHODS AND SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/943788 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16515800 [patent_doc_number] => 20200395058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SELF REFERENCE FOR FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/921860 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17637917 [patent_doc_number] => 11348646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Apparatus and method for managing program operation time and write latency in memory system [patent_app_type] => utility [patent_app_number] => 16/920165 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 17349 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17543910 [patent_doc_number] => 11309042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise [patent_app_type] => utility [patent_app_number] => 16/915289 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609056 [patent_doc_number] => 10910069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Manage source line bias to account for non-uniform resistance of memory cell source lines [patent_app_type] => utility [patent_app_number] => 16/909821 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 13614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16332059 [patent_doc_number] => 20200303025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => PROGRAMMING PROCESS COMBINING ADAPTIVE VERIFY WITH NORMAL AND SLOW PROGRAMMING SPEEDS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/893626 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16880907 [patent_doc_number] => 11031063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Word-line driver and method of operating a word-line driver [patent_app_type] => utility [patent_app_number] => 16/884143 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5445 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17121913 [patent_doc_number] => 11133053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Sensing and tuning for memory die power management [patent_app_type] => utility [patent_app_number] => 16/863967 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17637912 [patent_doc_number] => 11348641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/856137 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 16142 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16241344 [patent_doc_number] => 20200258578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => NAND TEMPERATURE DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/856955 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17308918 [patent_doc_number] => 11210028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Method for accessing flash memory module and associated flash memory controller and electronic device [patent_app_type] => utility [patent_app_number] => 16/856008 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715331 [patent_doc_number] => 20210082478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND A MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/852986 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16192764 [patent_doc_number] => 20200233613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/841335 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17128705 [patent_doc_number] => 20210303474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Command Optimization Through Intelligent Threshold Detection [patent_app_type] => utility [patent_app_number] => 16/835836 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746486 [patent_doc_number] => 10971487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/829918 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16447993 [patent_doc_number] => 10839924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/816898 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 12432 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16928042 [patent_doc_number] => 11049531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Nonvolatile memory device, operating method thereof, and data storage apparatus including the same [patent_app_type] => utility [patent_app_number] => 16/803446 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17000977 [patent_doc_number] => 11079784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system [patent_app_type] => utility [patent_app_number] => 16/801221 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13309 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801221 [rel_patent_id] =>[rel_patent_doc_number] =>)