Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15906247 [patent_doc_number] => 20200152644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Integrated Assemblies Having Ferroelectric Transistors with Heterostructure Active Regions [patent_app_type] => utility [patent_app_number] => 16/188432 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188432
Integrated assemblies having ferroelectric transistors with heterostructure active regions Nov 12, 2018 Issued
Array ( [id] => 17002339 [patent_doc_number] => 11081161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Sensing and tuning for memory die power management [patent_app_type] => utility [patent_app_number] => 16/185464 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14504 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185464 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185464
Sensing and tuning for memory die power management Nov 8, 2018 Issued
Array ( [id] => 15872995 [patent_doc_number] => 20200143901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Sensor for Performance Variation of Memory Read and Write Characteristics [patent_app_type] => utility [patent_app_number] => 16/183660 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183660
Sensor for performance variation of memory read and write characteristics Nov 6, 2018 Issued
Array ( [id] => 15890019 [patent_doc_number] => 10651368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Multi-bit-per-cell memory device based on the unidirectional spin hall magnetoresistance [patent_app_type] => utility [patent_app_number] => 16/170992 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7106 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170992
Multi-bit-per-cell memory device based on the unidirectional spin hall magnetoresistance Oct 24, 2018 Issued
Array ( [id] => 16279922 [patent_doc_number] => 10762960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Resistive random access memory device [patent_app_type] => utility [patent_app_number] => 16/158498 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/158498
Resistive random access memory device Oct 11, 2018 Issued
Array ( [id] => 16479349 [patent_doc_number] => 10854302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory system and memory control method [patent_app_type] => utility [patent_app_number] => 16/159410 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/159410
Memory system and memory control method Oct 11, 2018 Issued
Array ( [id] => 16417609 [patent_doc_number] => 10825509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Full-rail digital read compute-in-memory circuit [patent_app_type] => utility [patent_app_number] => 16/146932 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8036 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146932
Full-rail digital read compute-in-memory circuit Sep 27, 2018 Issued
Array ( [id] => 16432673 [patent_doc_number] => 10832766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Program verification time reduction in non-volatile memory devices [patent_app_type] => utility [patent_app_number] => 16/146814 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8184 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146814
Program verification time reduction in non-volatile memory devices Sep 27, 2018 Issued
Array ( [id] => 14842611 [patent_doc_number] => 20190279706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => REFRESH CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND REFRESH METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/145460 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145460
Refresh control circuit, semiconductor memory device, and refresh method thereof Sep 27, 2018 Issued
Array ( [id] => 15640815 [patent_doc_number] => 10593410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Reading circuit and method for a non-volatile memory device [patent_app_type] => utility [patent_app_number] => 16/145734 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145734
Reading circuit and method for a non-volatile memory device Sep 27, 2018 Issued
Array ( [id] => 13847477 [patent_doc_number] => 20190027223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/144597 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/144597
Semiconductor memory device Sep 26, 2018 Issued
Array ( [id] => 16201750 [patent_doc_number] => 10726925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Manage source line bias to account for non-uniform resistance of memory cell source lines [patent_app_type] => utility [patent_app_number] => 16/142386 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 13570 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142386
Manage source line bias to account for non-uniform resistance of memory cell source lines Sep 25, 2018 Issued
Array ( [id] => 14721927 [patent_doc_number] => 20190252027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => NON-VOLATILE MEMORY DEVICE AND A READ METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/141294 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141294
Non-volatile memory device and a read method thereof Sep 24, 2018 Issued
Array ( [id] => 13995175 [patent_doc_number] => 20190066745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => ADJUSTING INSTRUCTION DELAYS TO THE LATCH PATH IN DDR5 DRAM [patent_app_type] => utility [patent_app_number] => 16/137428 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137428
Adjusting instruction delays to the latch path in DDR5 DRAM Sep 19, 2018 Issued
Array ( [id] => 15427409 [patent_doc_number] => 10546639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Multifunctional memory cells [patent_app_type] => utility [patent_app_number] => 16/134603 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13602 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134603
Multifunctional memory cells Sep 17, 2018 Issued
Array ( [id] => 15184401 [patent_doc_number] => 20190362792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/132762 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132762
Semiconductor memory device Sep 16, 2018 Issued
Array ( [id] => 16186889 [patent_doc_number] => 10720225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Information processing apparatus, control method thereof, and storage mediumMD [patent_app_type] => utility [patent_app_number] => 16/131474 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11329 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16131474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/131474
Information processing apparatus, control method thereof, and storage mediumMD Sep 13, 2018 Issued
Array ( [id] => 15249789 [patent_doc_number] => 10510422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Memory devices with read level calibration [patent_app_type] => utility [patent_app_number] => 16/127085 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7021 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127085
Memory devices with read level calibration Sep 9, 2018 Issued
Array ( [id] => 14378971 [patent_doc_number] => 20190163398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/118412 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118412
Semiconductor memory Aug 29, 2018 Issued
Array ( [id] => 15169527 [patent_doc_number] => 10490266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device, electronic component, and electronic device [patent_app_type] => utility [patent_app_number] => 16/109851 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 59 [patent_no_of_words] => 22303 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109851
Semiconductor device, electronic component, and electronic device Aug 22, 2018 Issued
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