Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13908721 [patent_doc_number] => 20190043565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD AND SYSTEM FOR COMPENSATING FOR FLOATING GATE-TO-FLOATING GATE (FG-FG) INTERFERENCE IN FLASH MEMORY CELL READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/848948 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848948 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848948
Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations Dec 19, 2017 Issued
Array ( [id] => 15518937 [patent_doc_number] => 10566062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Memory device and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/841598 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2849 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841598
Memory device and method for operating the same Dec 13, 2017 Issued
Array ( [id] => 13349151 [patent_doc_number] => 20180226115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => MAGNETORESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/841454 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841454
Magnetoresistive memory device Dec 13, 2017 Issued
Array ( [id] => 15921599 [patent_doc_number] => 10658046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Memory device and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/841622 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3818 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841622 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841622
Memory device and method for operating the same Dec 13, 2017 Issued
Array ( [id] => 12188498 [patent_doc_number] => 20180047434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME' [patent_app_type] => utility [patent_app_number] => 15/794724 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794724
Apparatuses including multiple read modes and methods for same Oct 25, 2017 Issued
Array ( [id] => 12822829 [patent_doc_number] => 20180166115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => Word-Line Driver and Method of Operating a Word-Line Driver [patent_app_type] => utility [patent_app_number] => 15/725460 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725460
Word-line driver and method of operating a word-line driver Oct 4, 2017 Issued
Array ( [id] => 14827405 [patent_doc_number] => 10410713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-10 [patent_title] => Content addressable memory modeling in emulation and prototyping [patent_app_type] => utility [patent_app_number] => 15/724262 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8046 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724262
Content addressable memory modeling in emulation and prototyping Oct 2, 2017 Issued
Array ( [id] => 14555771 [patent_doc_number] => 10346347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Field-programmable crossbar array for reconfigurable computing [patent_app_type] => utility [patent_app_number] => 15/723668 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 9196 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723668 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723668
Field-programmable crossbar array for reconfigurable computing Oct 2, 2017 Issued
Array ( [id] => 13018773 [patent_doc_number] => 10032501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/715846 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14130 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715846
Semiconductor device Sep 25, 2017 Issued
Array ( [id] => 14491561 [patent_doc_number] => 10332578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/703054 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3342 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703054
Semiconductor device Sep 12, 2017 Issued
Array ( [id] => 14644003 [patent_doc_number] => 10366749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 15/703070 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 16005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703070
Memory system Sep 12, 2017 Issued
Array ( [id] => 14366471 [patent_doc_number] => 10304547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Memory device and clock training method thereof [patent_app_type] => utility [patent_app_number] => 15/700324 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9099 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700324
Memory device and clock training method thereof Sep 10, 2017 Issued
Array ( [id] => 14063541 [patent_doc_number] => 10236071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Dual-bit ROM cell with virtual ground line and programmable metal track [patent_app_type] => utility [patent_app_number] => 15/700152 [patent_app_country] => US [patent_app_date] => 2017-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9560 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700152
Dual-bit ROM cell with virtual ground line and programmable metal track Sep 9, 2017 Issued
Array ( [id] => 14603077 [patent_doc_number] => 10354732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => NAND temperature data management [patent_app_type] => utility [patent_app_number] => 15/690920 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13761 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690920 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690920
NAND temperature data management Aug 29, 2017 Issued
Array ( [id] => 12895555 [patent_doc_number] => 20180190360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DEVICE FOR DETECTING LEAKAGE CURRENT AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/690768 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690768
Device for detecting leakage current and memory device Aug 29, 2017 Issued
Array ( [id] => 13769023 [patent_doc_number] => 10176858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Adjusting instruction delays to the latch path in DDR5 DRAM [patent_app_type] => utility [patent_app_number] => 15/691394 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691394
Adjusting instruction delays to the latch path in DDR5 DRAM Aug 29, 2017 Issued
Array ( [id] => 14459363 [patent_doc_number] => 10325652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Cell programming verification [patent_app_type] => utility [patent_app_number] => 15/690148 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6204 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690148
Cell programming verification Aug 28, 2017 Issued
Array ( [id] => 14204611 [patent_doc_number] => 10269424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor memory apparatus [patent_app_type] => utility [patent_app_number] => 15/669689 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669689
Semiconductor memory apparatus Aug 3, 2017 Issued
Array ( [id] => 13893119 [patent_doc_number] => 10199111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-05 [patent_title] => Memory devices with read level calibration [patent_app_type] => utility [patent_app_number] => 15/669055 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6994 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669055
Memory devices with read level calibration Aug 3, 2017 Issued
Array ( [id] => 13272357 [patent_doc_number] => 10148269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-04 [patent_title] => Dynamic termination edge control [patent_app_type] => utility [patent_app_number] => 15/658276 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658276 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658276
Dynamic termination edge control Jul 23, 2017 Issued
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