
Minh D. Dinh
Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2825 |
| Total Applications | 480 |
| Issued Applications | 442 |
| Pending Applications | 36 |
| Abandoned Applications | 13 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13256699
[patent_doc_number] => 10141043
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-11-27
[patent_title] => DRAM and method for managing power thereof
[patent_app_type] => utility
[patent_app_number] => 15/657592
[patent_app_country] => US
[patent_app_date] => 2017-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6742
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657592
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/657592 | DRAM and method for managing power thereof | Jul 23, 2017 | Issued |
Array
(
[id] => 13799073
[patent_doc_number] => 20190013075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-10
[patent_title] => MULTIFUNCTIONAL MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 15/641736
[patent_app_country] => US
[patent_app_date] => 2017-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641736
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/641736 | Multifunctional memory cells | Jul 4, 2017 | Issued |
Array
(
[id] => 12129073
[patent_doc_number] => 20180012659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'Tunnel FET Based Non-Volatile Memory Boosted By Vertical Band-to-Band Tunneling'
[patent_app_type] => utility
[patent_app_number] => 15/641472
[patent_app_country] => US
[patent_app_date] => 2017-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 5648
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641472
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/641472 | Tunnel FET Based Non-Volatile Memory Boosted By Vertical Band-to-Band Tunneling | Jul 4, 2017 | Abandoned |
Array
(
[id] => 12263549
[patent_doc_number] => 20180082745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/640568
[patent_app_country] => US
[patent_app_date] => 2017-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 23027
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640568
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640568 | Semiconductor device | Jul 1, 2017 | Issued |
Array
(
[id] => 16279903
[patent_doc_number] => 10762939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Computer memory
[patent_app_type] => utility
[patent_app_number] => 15/640530
[patent_app_country] => US
[patent_app_date] => 2017-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7056
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640530
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640530 | Computer memory | Jun 30, 2017 | Issued |
Array
(
[id] => 13784949
[patent_doc_number] => 20190006013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => SELECTIVE BODY RESET OPERATION FOR THREE DIMENSIONAL (3D) NAND MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/640518
[patent_app_country] => US
[patent_app_date] => 2017-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10687
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640518
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640518 | Selective body reset operation for three dimensional (3D) NAND memory | Jun 30, 2017 | Issued |
Array
(
[id] => 13242531
[patent_doc_number] => 10134472
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-11-20
[patent_title] => Floating gate architecture for deep neural network application
[patent_app_type] => utility
[patent_app_number] => 15/640190
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 8215
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640190
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640190 | Floating gate architecture for deep neural network application | Jun 29, 2017 | Issued |
Array
(
[id] => 13201041
[patent_doc_number] => 10115440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Word line contact regions for three-dimensional non-volatile memory
[patent_app_type] => utility
[patent_app_number] => 15/625848
[patent_app_country] => US
[patent_app_date] => 2017-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 11710
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625848
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/625848 | Word line contact regions for three-dimensional non-volatile memory | Jun 15, 2017 | Issued |
Array
(
[id] => 13215161
[patent_doc_number] => 10121959
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-11-06
[patent_title] => FDSOI STT-MRAM design
[patent_app_type] => utility
[patent_app_number] => 15/625272
[patent_app_country] => US
[patent_app_date] => 2017-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3835
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625272
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/625272 | FDSOI STT-MRAM design | Jun 15, 2017 | Issued |
Array
(
[id] => 12154521
[patent_doc_number] => 20180025785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'ONE-TIME PROGRAMMABLE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/619300
[patent_app_country] => US
[patent_app_date] => 2017-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6946
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619300
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/619300 | One-time programmable memory device | Jun 8, 2017 | Issued |
Array
(
[id] => 13613073
[patent_doc_number] => 20180358086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => Write Operation Scheme for SRAM
[patent_app_type] => utility
[patent_app_number] => 15/619332
[patent_app_country] => US
[patent_app_date] => 2017-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619332
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/619332 | Write operation scheme for SRAM | Jun 8, 2017 | Issued |
Array
(
[id] => 14253147
[patent_doc_number] => 10276783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => Gate voltage controlled perpendicular spin orbit torque MRAM memory cell
[patent_app_type] => utility
[patent_app_number] => 15/618878
[patent_app_country] => US
[patent_app_date] => 2017-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 7026
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15618878
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/618878 | Gate voltage controlled perpendicular spin orbit torque MRAM memory cell | Jun 8, 2017 | Issued |
Array
(
[id] => 12649731
[patent_doc_number] => 20180108408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => RESISTIVE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/617090
[patent_app_country] => US
[patent_app_date] => 2017-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6035
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617090
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/617090 | Resistive memory device and memory system including the same | Jun 7, 2017 | Issued |
Array
(
[id] => 14526363
[patent_doc_number] => 10340453
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-02
[patent_title] => Forming and operating memory devices that utilize correlated electron material (CEM)
[patent_app_type] => utility
[patent_app_number] => 15/610288
[patent_app_country] => US
[patent_app_date] => 2017-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 12964
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610288
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/610288 | Forming and operating memory devices that utilize correlated electron material (CEM) | May 30, 2017 | Issued |
Array
(
[id] => 12738268
[patent_doc_number] => 20180137923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => CIRCUITS AND METHODS OF REFERENCE-CURRENT GENERATION FOR FLASH
[patent_app_type] => utility
[patent_app_number] => 15/609414
[patent_app_country] => US
[patent_app_date] => 2017-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 332
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609414
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/609414 | Circuits and methods of reference-current generation for flash | May 30, 2017 | Issued |
Array
(
[id] => 13581481
[patent_doc_number] => 20180342289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-29
[patent_title] => AGING AWARE DYNAMIC KEEPER APPARATUS AND ASSOCIATED METHOD
[patent_app_type] => utility
[patent_app_number] => 15/604519
[patent_app_country] => US
[patent_app_date] => 2017-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9971
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/604519 | Aging aware dynamic keeper apparatus and associated method | May 23, 2017 | Issued |
Array
(
[id] => 14397339
[patent_doc_number] => 10311958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Array of three-gate flash memory cells with individual memory cell read, program and erase
[patent_app_type] => utility
[patent_app_number] => 15/593231
[patent_app_country] => US
[patent_app_date] => 2017-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3764
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593231
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/593231 | Array of three-gate flash memory cells with individual memory cell read, program and erase | May 10, 2017 | Issued |
Array
(
[id] => 15806945
[patent_doc_number] => 20200126615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => READ-OUT CIRCUIT AND READ-OUT METHOD FOR THREE-DIMENSIONAL MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/739723
[patent_app_country] => US
[patent_app_date] => 2017-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9693
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739723
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/739723 | Read-out circuit and read-out method for three-dimensional memory | Apr 24, 2017 | Issued |
Array
(
[id] => 13976301
[patent_doc_number] => 10217515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Programming memory devices
[patent_app_type] => utility
[patent_app_number] => 15/477048
[patent_app_country] => US
[patent_app_date] => 2017-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8362
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477048
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/477048 | Programming memory devices | Mar 31, 2017 | Issued |
Array
(
[id] => 12019499
[patent_doc_number] => 09812207
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 15/457137
[patent_app_country] => US
[patent_app_date] => 2017-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 15387
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457137
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/457137 | Semiconductor memory device | Mar 12, 2017 | Issued |