Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11027127 [patent_doc_number] => 20160224082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'MEMORY CELL AND STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/023066 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 13145 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15023066 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/023066
Memory cell and storage device Sep 17, 2014 Issued
Array ( [id] => 10425893 [patent_doc_number] => 20150310904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/263632 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14263632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/263632
SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY Apr 27, 2014 Abandoned
Array ( [id] => 10294285 [patent_doc_number] => 20150179285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'DETECTING DEFECTIVE CONNECTIONS IN STACKED MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/248480 [patent_app_country] => US [patent_app_date] => 2014-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6200 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248480 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248480
Detecting defective connections in stacked memory devices Apr 8, 2014 Issued
Array ( [id] => 11385737 [patent_doc_number] => 20170011793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 15/115464 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10428 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15115464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/115464
Apparatus for adaptive write assist for memory Mar 4, 2014 Issued
Array ( [id] => 9697963 [patent_doc_number] => 20140247648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/195729 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195729 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195729
Electronic device having resistance element Mar 2, 2014 Issued
Array ( [id] => 10502248 [patent_doc_number] => 09230650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Semiconductor device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 14/166677 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166677
Semiconductor device and method for operating the same Jan 27, 2014 Issued
Array ( [id] => 10321573 [patent_doc_number] => 20150206577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 14/162639 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162639
Hybrid approach to write assist for memory array Jan 22, 2014 Issued
Array ( [id] => 10502246 [patent_doc_number] => 09230649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Non-volatile ternary content-addressable memory 4T2R cell with RC-delay search' [patent_app_type] => utility [patent_app_number] => 14/159005 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159005 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159005
Non-volatile ternary content-addressable memory 4T2R cell with RC-delay search Jan 19, 2014 Issued
Array ( [id] => 10309193 [patent_doc_number] => 20150194194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'SINGLE-ENDED SENSING CIRCUITS FOR SIGNAL LINES' [patent_app_type] => utility [patent_app_number] => 14/146793 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146793 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146793
Single ended sensing circuits for signal lines Jan 2, 2014 Issued
Array ( [id] => 10537523 [patent_doc_number] => 09263157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Detecting defective connections in stacked memory devices' [patent_app_type] => utility [patent_app_number] => 14/138838 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6202 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138838 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138838
Detecting defective connections in stacked memory devices Dec 22, 2013 Issued
Array ( [id] => 10645418 [patent_doc_number] => 09362293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'CT-NOR differential bitline sensing architecture' [patent_app_type] => utility [patent_app_number] => 14/135863 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135863 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/135863
CT-NOR differential bitline sensing architecture Dec 19, 2013 Issued
Array ( [id] => 10270017 [patent_doc_number] => 20150155014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'MEMORY CIRCUITRY INCLUDING READ VOLTAGE BOOST' [patent_app_type] => utility [patent_app_number] => 14/093041 [patent_app_country] => US [patent_app_date] => 2013-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093041 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093041
Memory circuitry including read voltage boost Nov 28, 2013 Issued
Array ( [id] => 10213285 [patent_doc_number] => 20150098277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'Data Strobe Generation' [patent_app_type] => utility [patent_app_number] => 14/045644 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2856 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045644
Data strobe generation Oct 2, 2013 Issued
Array ( [id] => 10918201 [patent_doc_number] => 20140321220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING EXTERNAL VOLTAGE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/018732 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018732
Semiconductor memory apparatus and method of controlling external voltage using the same Sep 4, 2013 Issued
Array ( [id] => 10144837 [patent_doc_number] => 09177649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Flash memory circuit' [patent_app_type] => utility [patent_app_number] => 14/017770 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5464 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017770
Flash memory circuit Sep 3, 2013 Issued
Array ( [id] => 10144830 [patent_doc_number] => 09177641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 14/018306 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5272 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018306
Memory device Sep 3, 2013 Issued
Array ( [id] => 9856392 [patent_doc_number] => 20150036409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL USING MAGNETIC TUNNEL JUNCTION CELLS' [patent_app_type] => utility [patent_app_number] => 13/953771 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8860 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953771 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953771
System and method to provide a reference cell using magnetic tunnel junction cells Jul 29, 2013 Issued
Array ( [id] => 9305218 [patent_doc_number] => 20140043892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE RESISTANCE MEMORY AND OPERATING METHOD' [patent_app_type] => utility [patent_app_number] => 13/954161 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9624 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954161 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954161
Semiconductor memory device having variable resistance memory and operating method Jul 29, 2013 Issued
Array ( [id] => 10502255 [patent_doc_number] => 09230657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Memory device with erase mode memory cells' [patent_app_type] => utility [patent_app_number] => 13/952591 [patent_app_country] => US [patent_app_date] => 2013-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 9983 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13952591 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/952591
Memory device with erase mode memory cells Jul 26, 2013 Issued
Array ( [id] => 11452968 [patent_doc_number] => 09576616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Non-volatile memory with overwrite capability and low write amplification' [patent_app_type] => utility [patent_app_number] => 13/952467 [patent_app_country] => US [patent_app_date] => 2013-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13952467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/952467
Non-volatile memory with overwrite capability and low write amplification Jul 25, 2013 Issued
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