Search

Minh D. Dinh

Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
480
Issued Applications
442
Pending Applications
36
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10603845 [patent_doc_number] => 09324414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Selective dual cycle write operation for a self-timed memory' [patent_app_type] => utility [patent_app_number] => 13/949449 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12740 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949449 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949449
Selective dual cycle write operation for a self-timed memory Jul 23, 2013 Issued
Array ( [id] => 10531059 [patent_doc_number] => 09257199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Canary circuit with passgate transistor variation' [patent_app_type] => utility [patent_app_number] => 13/949343 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3769 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949343
Canary circuit with passgate transistor variation Jul 23, 2013 Issued
Array ( [id] => 10937935 [patent_doc_number] => 20140340957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'NON-VOLATILE LATCH USING SPIN-TRANSFER TORQUE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/894266 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894266 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894266
Non-volatile latch using spin-transfer torque memory device May 13, 2013 Issued
Array ( [id] => 10931203 [patent_doc_number] => 20140334224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'REFERENCE VOLTAGE MODIFICATION IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/889528 [patent_app_country] => US [patent_app_date] => 2013-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13889528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/889528
Reference voltage modification in a memory device May 7, 2013 Issued
Array ( [id] => 10603880 [patent_doc_number] => 09324450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'NAND flash memory' [patent_app_type] => utility [patent_app_number] => 13/799215 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10736 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799215
NAND flash memory Mar 12, 2013 Issued
Array ( [id] => 9080285 [patent_doc_number] => 20130265815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'METHOD OF READING DATA STORED IN FUSE DEVICE AND APPARATUSES USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/798679 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7157 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/798679
Method of reading data stored in fuse device and apparatuses using the same Mar 12, 2013 Issued
Array ( [id] => 10531012 [patent_doc_number] => 09257153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Current monitoring circuit for memory wakeup time' [patent_app_type] => utility [patent_app_number] => 13/798991 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798991 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/798991
Current monitoring circuit for memory wakeup time Mar 12, 2013 Issued
Array ( [id] => 10131832 [patent_doc_number] => 09165673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Semiconductor memory device including sensing verification unit' [patent_app_type] => utility [patent_app_number] => 13/795567 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 8820 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795567
Semiconductor memory device including sensing verification unit Mar 11, 2013 Issued
Array ( [id] => 9614793 [patent_doc_number] => 20140204650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'NONVOLATILE RESISTIVE MEMORY DEVICE AND WRITING METHOD' [patent_app_type] => utility [patent_app_number] => 13/797089 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13797089 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/797089
Nonvolatile resistive memory device and writing method Mar 11, 2013 Issued
Array ( [id] => 9080310 [patent_doc_number] => 20130265840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING' [patent_app_type] => utility [patent_app_number] => 13/796797 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6006 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796797 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796797
SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING Mar 11, 2013 Abandoned
Array ( [id] => 10576754 [patent_doc_number] => 09299404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Methods and apparatus for performing boosted bit line precharge' [patent_app_type] => utility [patent_app_number] => 13/796859 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6824 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796859
Methods and apparatus for performing boosted bit line precharge Mar 11, 2013 Issued
Array ( [id] => 10003861 [patent_doc_number] => 09047959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-02 [patent_title] => 'Data storage device, memory control method, and electronic device with data storage device' [patent_app_type] => utility [patent_app_number] => 13/795419 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 4600 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795419
Data storage device, memory control method, and electronic device with data storage device Mar 11, 2013 Issued
Array ( [id] => 10178645 [patent_doc_number] => 09208856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Multiport memory with matching address control' [patent_app_type] => utility [patent_app_number] => 13/795789 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795789 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795789
Multiport memory with matching address control Mar 11, 2013 Issued
Array ( [id] => 9718600 [patent_doc_number] => 20140254298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'VARIABLE DYNAMIC MEMORY REFRESH' [patent_app_type] => utility [patent_app_number] => 13/794563 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5541 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13794563 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/794563
Variable dynamic memory refresh Mar 10, 2013 Issued
Array ( [id] => 10131814 [patent_doc_number] => 09165656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Non-volatile storage with shared bit lines and flat memory cells' [patent_app_type] => utility [patent_app_number] => 13/793925 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 11145 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793925 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793925
Non-volatile storage with shared bit lines and flat memory cells Mar 10, 2013 Issued
Array ( [id] => 9133426 [patent_doc_number] => 20130294140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/793457 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793457 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793457
Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same Mar 10, 2013 Issued
Array ( [id] => 9489752 [patent_doc_number] => 20140140158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'PRE-CHARGING A DATA LINE' [patent_app_type] => utility [patent_app_number] => 13/793815 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793815
Pre-charging a data line Mar 10, 2013 Issued
Array ( [id] => 9718540 [patent_doc_number] => 20140254238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'SENSING DATA IN RESISTIVE SWITCHING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/793685 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12854 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793685 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793685
Sensing data in resistive switching memory devices Mar 10, 2013 Issued
Array ( [id] => 11214536 [patent_doc_number] => 09443574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Memory architecture' [patent_app_type] => utility [patent_app_number] => 13/793945 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6021 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793945 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793945
Memory architecture Mar 10, 2013 Issued
Array ( [id] => 10010287 [patent_doc_number] => 09053810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Defect or program disturb detection with full data recovery capability' [patent_app_type] => utility [patent_app_number] => 13/790469 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 50 [patent_no_of_words] => 15776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790469
Defect or program disturb detection with full data recovery capability Mar 7, 2013 Issued
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