Search

Minh D. Dinh

Examiner (ID: 16802, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827
Total Applications
472
Issued Applications
435
Pending Applications
37
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18712573 [patent_doc_number] => 20230335206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => FUSE BLOCK UNIT AND FUSE BLOCK SYSTEM AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/191986 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191986
Fuse block unit and fuse block system and memory device Mar 28, 2023 Issued
Array ( [id] => 19467706 [patent_doc_number] => 20240321376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset [patent_app_type] => utility [patent_app_number] => 18/123852 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123852
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset Mar 19, 2023 Abandoned
Array ( [id] => 19467706 [patent_doc_number] => 20240321376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset [patent_app_type] => utility [patent_app_number] => 18/123852 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123852
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset Mar 19, 2023 Abandoned
Array ( [id] => 19452398 [patent_doc_number] => 20240312528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => FEATURE BASED READ THRESHOLD ESTIMATION IN NAND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 18/122758 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122758
FEATURE BASED READ THRESHOLD ESTIMATION IN NAND FLASH MEMORY Mar 16, 2023 Issued
Array ( [id] => 18820791 [patent_doc_number] => 20230395132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SRAM CELL CONFIGURED TO PERFORM MULTIPLY-ACCUMULATE (MAC) OPERATION ON MULTI-BIT DATA BASED ON CHARGE SHARING AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/180623 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180623
SRAM cell configured to perform multiply-accumulate (MAC) operation on multi-bit data based on charge sharing and method of operating the same Mar 7, 2023 Issued
Array ( [id] => 20189577 [patent_doc_number] => 12400699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Three-dimensional non-volatile memory floorplan architecture [patent_app_type] => utility [patent_app_number] => 18/119180 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119180
Three-dimensional non-volatile memory floorplan architecture Mar 7, 2023 Issued
Array ( [id] => 20189577 [patent_doc_number] => 12400699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Three-dimensional non-volatile memory floorplan architecture [patent_app_type] => utility [patent_app_number] => 18/119180 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119180
Three-dimensional non-volatile memory floorplan architecture Mar 7, 2023 Issued
Array ( [id] => 19858055 [patent_doc_number] => 12260905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => SRAM with improved write performance and write operation method thereof [patent_app_type] => utility [patent_app_number] => 18/168943 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6112 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168943
SRAM with improved write performance and write operation method thereof Feb 13, 2023 Issued
Array ( [id] => 20345795 [patent_doc_number] => 12469530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Circuit and method for data processing, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/163861 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7677 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163861
Circuit and method for data processing, and semiconductor memory Feb 1, 2023 Issued
Array ( [id] => 18865621 [patent_doc_number] => 20230420058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/099808 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099808
NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAME Jan 19, 2023 Pending
Array ( [id] => 18865621 [patent_doc_number] => 20230420058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/099808 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099808
NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAME Jan 19, 2023 Pending
Array ( [id] => 18631483 [patent_doc_number] => 20230290385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => BIAS GENERATION CIRCUIT AND MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/154937 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154937
Bias generation circuit and memory circuit Jan 15, 2023 Issued
Array ( [id] => 18360302 [patent_doc_number] => 20230141893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SELECTION OF READ OFFSET VALUES IN A MEMORY SUB-SYSTEM BASED ON TEMPERATURE AND TIME TO PROGRAM LEVELS [patent_app_type] => utility [patent_app_number] => 18/093646 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093646
Selection of read offset values in a memory sub-system based on temperature and time to program levels Jan 4, 2023 Issued
Array ( [id] => 18379413 [patent_doc_number] => 20230154502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => Low Power Memory System Using Dual Input-Output Voltage Supplies [patent_app_type] => utility [patent_app_number] => 18/150155 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150155
Low power memory system using dual input-output voltage supplies Jan 3, 2023 Issued
Array ( [id] => 18310003 [patent_doc_number] => 20230113903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/080696 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080696
Resistive random access memory device Dec 12, 2022 Issued
Array ( [id] => 18943173 [patent_doc_number] => 20240038312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => MEMORY DEVICE FOR EFFECTIVELY CHECKING PROGRAM STATE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/073751 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073751 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073751
Memory device for effectively checking program state and operation method thereof Dec 1, 2022 Issued
Array ( [id] => 19972232 [patent_doc_number] => 12340850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Source bias temperature compensation for read and program verify operations on a memory device [patent_app_type] => utility [patent_app_number] => 17/994907 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994907
Source bias temperature compensation for read and program verify operations on a memory device Nov 27, 2022 Issued
Array ( [id] => 18251362 [patent_doc_number] => 20230078401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/989168 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989168
Managing programming convergence associated with memory cells of a memory sub-system Nov 16, 2022 Issued
Array ( [id] => 18912062 [patent_doc_number] => 11875041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor device and semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/988081 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 12613 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988081
Semiconductor device and semiconductor storage device Nov 15, 2022 Issued
Array ( [id] => 19765731 [patent_doc_number] => 12224030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/987435 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987435
Memory system Nov 14, 2022 Issued
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