Search

Minh D. Dinh

Examiner (ID: 15854, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
494
Issued Applications
460
Pending Applications
27
Abandoned Applications
14

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19740943 [patent_doc_number] => 12217782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Current steering in reading magnetic tunnel junction [patent_app_type] => utility [patent_app_number] => 18/332674 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332674
Current steering in reading magnetic tunnel junction Jun 8, 2023 Issued
Array ( [id] => 18820761 [patent_doc_number] => 20230395102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => BIT LINE SENSE AMPLIFIER AND BIT LINE SENSING METHOD OF SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/205057 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205057
Bit line sense amplifier and bit line sensing method of semiconductor memory device Jun 1, 2023 Issued
Array ( [id] => 18974938 [patent_doc_number] => 20240055030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => STORAGE DEVICES DETECTING INTERNAL TEMPERATURE AND DEFECTS BY USING TEMPERATURE SENSORS AND METHODS OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/204972 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204972
Storage devices detecting internal temperature and defects by using temperature sensors and methods of operating the same Jun 1, 2023 Issued
Array ( [id] => 20345836 [patent_doc_number] => 12469571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Method of operating a controller and a memory device related to recovering data [patent_app_type] => utility [patent_app_number] => 18/327759 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327759
Method of operating a controller and a memory device related to recovering data May 31, 2023 Issued
Array ( [id] => 19620096 [patent_doc_number] => 20240405776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => LEVEL-SHIFTER HAVING A WIDE OPERATING RANGE, A FAST OUTPUT FALL DELAY AND IMPROVED RISE TIME [patent_app_type] => utility [patent_app_number] => 18/326539 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326539
Level-shifter having a wide operating range, a fast output fall delay and improved rise time May 30, 2023 Issued
Array ( [id] => 19980000 [patent_doc_number] => 12347486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Forming method of resistive random-access memory array [patent_app_type] => utility [patent_app_number] => 18/201213 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201213
Forming method of resistive random-access memory array May 23, 2023 Issued
Array ( [id] => 19589380 [patent_doc_number] => 20240386937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SWITCHED-CAPACITOR VOLTAGE CONVERTER WITH SELECTIVE DECOUPLING CAPACITANCE [patent_app_type] => utility [patent_app_number] => 18/318659 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318659
SWITCHED-CAPACITOR VOLTAGE CONVERTER WITH SELECTIVE DECOUPLING CAPACITANCE May 15, 2023 Pending
Array ( [id] => 19574848 [patent_doc_number] => 20240379140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => CROSSBAR CIRCUITS UTILIZING CURRENT-MODE DIGITAL-TO-ANALOG CONVERTERS [patent_app_type] => utility [patent_app_number] => 18/316946 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316946
Crossbar circuits utilizing current-mode digital-to-analog converters May 11, 2023 Issued
Array ( [id] => 19559661 [patent_doc_number] => 20240371453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => MEMORY DEVICE FOR PERFORMING IN-MEMORY COMPUTATION AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/312630 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312630
Memory device for performing in-memory computation and operating method thereof May 4, 2023 Issued
Array ( [id] => 19452425 [patent_doc_number] => 20240312555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 18/303580 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303580
Memory chip Apr 19, 2023 Issued
Array ( [id] => 18868057 [patent_doc_number] => 20230422494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ONE-TIME PROGRAMMABLE MEMORY CELL AND MEMORY THEREOF [patent_app_type] => utility [patent_app_number] => 18/301473 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301473
One-time programmable memory cell and memory thereof Apr 16, 2023 Issued
Array ( [id] => 18712573 [patent_doc_number] => 20230335206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => FUSE BLOCK UNIT AND FUSE BLOCK SYSTEM AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/191986 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191986
Fuse block unit and fuse block system and memory device Mar 28, 2023 Issued
Array ( [id] => 19467706 [patent_doc_number] => 20240321376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset [patent_app_type] => utility [patent_app_number] => 18/123852 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123852
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset Mar 19, 2023 Abandoned
Array ( [id] => 19452398 [patent_doc_number] => 20240312528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => FEATURE BASED READ THRESHOLD ESTIMATION IN NAND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 18/122758 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122758
Feature based read threshold estimation in NAND flash memory Mar 16, 2023 Issued
Array ( [id] => 18820791 [patent_doc_number] => 20230395132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SRAM CELL CONFIGURED TO PERFORM MULTIPLY-ACCUMULATE (MAC) OPERATION ON MULTI-BIT DATA BASED ON CHARGE SHARING AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/180623 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180623
SRAM cell configured to perform multiply-accumulate (MAC) operation on multi-bit data based on charge sharing and method of operating the same Mar 7, 2023 Issued
Array ( [id] => 20189577 [patent_doc_number] => 12400699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Three-dimensional non-volatile memory floorplan architecture [patent_app_type] => utility [patent_app_number] => 18/119180 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119180
Three-dimensional non-volatile memory floorplan architecture Mar 7, 2023 Issued
Array ( [id] => 19858055 [patent_doc_number] => 12260905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => SRAM with improved write performance and write operation method thereof [patent_app_type] => utility [patent_app_number] => 18/168943 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6112 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168943
SRAM with improved write performance and write operation method thereof Feb 13, 2023 Issued
Array ( [id] => 20345795 [patent_doc_number] => 12469530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Circuit and method for data processing, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/163861 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7677 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163861
Circuit and method for data processing, and semiconductor memory Feb 1, 2023 Issued
Array ( [id] => 20455775 [patent_doc_number] => 12518835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Nonvolatile memory device and method of controlling read operation of the same [patent_app_type] => utility [patent_app_number] => 18/099808 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 10294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099808
Nonvolatile memory device and method of controlling read operation of the same Jan 19, 2023 Issued
Array ( [id] => 18631483 [patent_doc_number] => 20230290385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => BIAS GENERATION CIRCUIT AND MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/154937 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154937
Bias generation circuit and memory circuit Jan 15, 2023 Issued
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