Search

Minh D. Dinh

Examiner (ID: 15854, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
494
Issued Applications
460
Pending Applications
27
Abandoned Applications
14

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18360302 [patent_doc_number] => 20230141893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SELECTION OF READ OFFSET VALUES IN A MEMORY SUB-SYSTEM BASED ON TEMPERATURE AND TIME TO PROGRAM LEVELS [patent_app_type] => utility [patent_app_number] => 18/093646 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093646
Selection of read offset values in a memory sub-system based on temperature and time to program levels Jan 4, 2023 Issued
Array ( [id] => 18379413 [patent_doc_number] => 20230154502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => Low Power Memory System Using Dual Input-Output Voltage Supplies [patent_app_type] => utility [patent_app_number] => 18/150155 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150155
Low power memory system using dual input-output voltage supplies Jan 3, 2023 Issued
Array ( [id] => 19773112 [patent_doc_number] => 20250054538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SUPERCONDUCTING BIPOLAR THERMOELECTRIC MEMORY AND METHOD FOR WRITING A SUPERCONDUCTING BIPOLAR THERMOELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 18/721641 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18721641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/721641
SUPERCONDUCTING BIPOLAR THERMOELECTRIC MEMORY AND METHOD FOR WRITING A SUPERCONDUCTING BIPOLAR THERMOELECTRIC MEMORY Dec 19, 2022 Pending
Array ( [id] => 18310003 [patent_doc_number] => 20230113903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/080696 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080696
Resistive random access memory device Dec 12, 2022 Issued
Array ( [id] => 18943173 [patent_doc_number] => 20240038312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => MEMORY DEVICE FOR EFFECTIVELY CHECKING PROGRAM STATE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/073751 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073751 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073751
Memory device for effectively checking program state and operation method thereof Dec 1, 2022 Issued
Array ( [id] => 19972232 [patent_doc_number] => 12340850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Source bias temperature compensation for read and program verify operations on a memory device [patent_app_type] => utility [patent_app_number] => 17/994907 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994907
Source bias temperature compensation for read and program verify operations on a memory device Nov 27, 2022 Issued
Array ( [id] => 18251362 [patent_doc_number] => 20230078401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/989168 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989168
Managing programming convergence associated with memory cells of a memory sub-system Nov 16, 2022 Issued
Array ( [id] => 18912062 [patent_doc_number] => 11875041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor device and semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/988081 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 12613 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988081
Semiconductor device and semiconductor storage device Nov 15, 2022 Issued
Array ( [id] => 19765731 [patent_doc_number] => 12224030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/987435 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987435
Memory system Nov 14, 2022 Issued
Array ( [id] => 18209329 [patent_doc_number] => 20230055589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => Superconductive Memory Cells and Devices [patent_app_type] => utility [patent_app_number] => 17/967778 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967778
Superconductive memory cells and devices Oct 16, 2022 Issued
Array ( [id] => 18789019 [patent_doc_number] => 20230377627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE FOR EXECUTING A SMART REFRESH OPERATION AND A SMART REFRESH METHOD [patent_app_type] => utility [patent_app_number] => 17/964718 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964718
Semiconductor device for executing a smart refresh operation and a smart refresh method Oct 11, 2022 Issued
Array ( [id] => 19153599 [patent_doc_number] => 11978521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods [patent_app_type] => utility [patent_app_number] => 17/937532 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937532
Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods Oct 2, 2022 Issued
Array ( [id] => 18279858 [patent_doc_number] => 20230095330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Multi-Output Look-Up Table (LUT) for Use in Coarse-Grained Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) Chip [patent_app_type] => utility [patent_app_number] => 17/952248 [patent_app_country] => US [patent_app_date] => 2022-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 145346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952248
Multi-output look-up table (LUT) for use in coarse-grained field-programmable-gate-array (FPGA) integrated-circuit (IC) chip Sep 23, 2022 Issued
Array ( [id] => 18285400 [patent_doc_number] => 20230100872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => INTEGRATED CIRCUIT COMPRISING A NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/932694 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932694
Integrated circuit comprising a non-volatile memory Sep 15, 2022 Issued
Array ( [id] => 19596805 [patent_doc_number] => 12154658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Data output control circuit and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 17/941719 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9285 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941719
Data output control circuit and semiconductor device including the same Sep 8, 2022 Issued
Array ( [id] => 19414518 [patent_doc_number] => 12080352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory system controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/902279 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 11855 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902279
Memory system controlling nonvolatile memory Sep 1, 2022 Issued
Array ( [id] => 18679525 [patent_doc_number] => 20230317181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/902754 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902754
Semiconductor storage device and memory system Sep 1, 2022 Issued
Array ( [id] => 18439689 [patent_doc_number] => 20230186984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/896929 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896929
Semiconductor memory device Aug 25, 2022 Issued
Array ( [id] => 19926024 [patent_doc_number] => 12300316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Cascoded sense amplifiers for self-selecting memory [patent_app_type] => utility [patent_app_number] => 17/896963 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896963
Cascoded sense amplifiers for self-selecting memory Aug 25, 2022 Issued
Array ( [id] => 18990818 [patent_doc_number] => 20240062787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SRAM POWER SWITCHING WITH REDUCED LEAKAGE, NOISE REJECTION, AND SUPPLY FAULT TOLERANCE [patent_app_type] => utility [patent_app_number] => 17/891858 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891858
SRAM power switching with reduced leakage, noise rejection, and supply fault tolerance Aug 18, 2022 Issued
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