Search

Minh D. Dinh

Examiner (ID: 16802, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827
Total Applications
472
Issued Applications
435
Pending Applications
37
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18209329 [patent_doc_number] => 20230055589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => Superconductive Memory Cells and Devices [patent_app_type] => utility [patent_app_number] => 17/967778 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967778
Superconductive memory cells and devices Oct 16, 2022 Issued
Array ( [id] => 18789019 [patent_doc_number] => 20230377627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE FOR EXECUTING A SMART REFRESH OPERATION AND A SMART REFRESH METHOD [patent_app_type] => utility [patent_app_number] => 17/964718 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964718
Semiconductor device for executing a smart refresh operation and a smart refresh method Oct 11, 2022 Issued
Array ( [id] => 19153599 [patent_doc_number] => 11978521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods [patent_app_type] => utility [patent_app_number] => 17/937532 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937532
Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods Oct 2, 2022 Issued
Array ( [id] => 18279858 [patent_doc_number] => 20230095330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Multi-Output Look-Up Table (LUT) for Use in Coarse-Grained Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) Chip [patent_app_type] => utility [patent_app_number] => 17/952248 [patent_app_country] => US [patent_app_date] => 2022-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 145346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952248
Multi-Output Look-Up Table (LUT) for Use in Coarse-Grained Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) Chip Sep 23, 2022 Pending
Array ( [id] => 18285400 [patent_doc_number] => 20230100872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => INTEGRATED CIRCUIT COMPRISING A NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/932694 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932694
Integrated circuit comprising a non-volatile memory Sep 15, 2022 Issued
Array ( [id] => 19596805 [patent_doc_number] => 12154658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Data output control circuit and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 17/941719 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9285 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941719
Data output control circuit and semiconductor device including the same Sep 8, 2022 Issued
Array ( [id] => 19414518 [patent_doc_number] => 12080352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory system controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/902279 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 11855 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902279
Memory system controlling nonvolatile memory Sep 1, 2022 Issued
Array ( [id] => 18679525 [patent_doc_number] => 20230317181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/902754 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902754
Semiconductor storage device and memory system Sep 1, 2022 Issued
Array ( [id] => 18439689 [patent_doc_number] => 20230186984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/896929 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896929
Semiconductor memory device Aug 25, 2022 Issued
Array ( [id] => 19926024 [patent_doc_number] => 12300316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Cascoded sense amplifiers for self-selecting memory [patent_app_type] => utility [patent_app_number] => 17/896963 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896963
Cascoded sense amplifiers for self-selecting memory Aug 25, 2022 Issued
Array ( [id] => 18990818 [patent_doc_number] => 20240062787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SRAM POWER SWITCHING WITH REDUCED LEAKAGE, NOISE REJECTION, AND SUPPLY FAULT TOLERANCE [patent_app_type] => utility [patent_app_number] => 17/891858 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891858
SRAM power switching with reduced leakage, noise rejection, and supply fault tolerance Aug 18, 2022 Issued
Array ( [id] => 18789063 [patent_doc_number] => 20230377676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => INTEGRATED CIRCUIT AND OPERATION METHOD AND INSPECTION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/883607 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883607
Integrated circuit and operation method and inspection method thereof Aug 8, 2022 Issued
Array ( [id] => 18943155 [patent_doc_number] => 20240038294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => PROGRAMMING AND READING CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/878200 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878200
Programming and reading circuit for dynamic random access memory Jul 31, 2022 Issued
Array ( [id] => 18943159 [patent_doc_number] => 20240038298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Josephson Static Random Access Memory [patent_app_type] => utility [patent_app_number] => 17/815358 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815358
Josephson static random access memory Jul 26, 2022 Issued
Array ( [id] => 18198710 [patent_doc_number] => 20230052229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME [patent_app_type] => utility [patent_app_number] => 17/814790 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814790
Apparatuses including multiple read modes and methods for same Jul 24, 2022 Issued
Array ( [id] => 17992982 [patent_doc_number] => 20220359019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => INTELLIGENT CHARGE PUMP ARCHITECTURE FOR FLASH ARRAY [patent_app_type] => utility [patent_app_number] => 17/870714 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870714
Intelligent charge pump architecture for flash array Jul 20, 2022 Issued
Array ( [id] => 18898339 [patent_doc_number] => 20240013824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Data transmission apparatus and method having clock gating mechanism [patent_app_type] => utility [patent_app_number] => 17/861424 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861424
Data transmission apparatus and method having clock gating mechanism Jul 10, 2022 Issued
Array ( [id] => 18142676 [patent_doc_number] => 20230016520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => STRATEGIC MEMORY CELL RELIABILITY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/861233 [patent_app_country] => US [patent_app_date] => 2022-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861233
Strategic memory cell reliability management Jul 9, 2022 Issued
Array ( [id] => 18138913 [patent_doc_number] => 20230012748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => MEMORY CIRCUIT COMPRISING A PLURALITY OF 1T1R MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/860607 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860607
Memory circuit comprising a plurality of 1T1R memory cells Jul 7, 2022 Issued
Array ( [id] => 18820820 [patent_doc_number] => 20230395161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/860690 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860690
Managing compensation for charge coupling and lateral migration in memory devices Jul 7, 2022 Issued
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