Minh D. Dinh

Array ( [id] => 18935223 [patent_doc_number] => 11887661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Cross-point pillar architecture for memory arrays [patent_app_type] => utility [patent_app_number] => 17/647578 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 24827 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17676352 [patent_doc_number] => 20220189519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => Memory Subsystem Calibration Using Substitute Results [patent_app_type] => utility [patent_app_number] => 17/646741 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19045162 [patent_doc_number] => 11934271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/564925 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 43 [patent_no_of_words] => 26087 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18472735 [patent_doc_number] => 20230207023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PAGE GROUP READ VOLTAGE THRESHOLD CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/562772 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17691840 [patent_doc_number] => 20220199133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SECURE MEMORY [patent_app_type] => utility [patent_app_number] => 17/556039 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18439690 [patent_doc_number] => 20230186985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => TECHNOLOGIES FOR DYNAMIC CURRENT MIRROR BIASING FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/550330 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19079282 [patent_doc_number] => 11948657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Sense amplifier layout designs and related apparatuses and methods [patent_app_type] => utility [patent_app_number] => 17/547574 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12668 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17509248 [patent_doc_number] => 20220102351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => APPARATUSES INCLUDING ELONGATE PILLARS OF ACCESS DEVICES [patent_app_type] => utility [patent_app_number] => 17/643316 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18112669 [patent_doc_number] => 20230005549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/534210 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18562748 [patent_doc_number] => 11727998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Memory system and memory control method [patent_app_type] => utility [patent_app_number] => 17/512394 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18339168 [patent_doc_number] => 20230131117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DATA CONVERSION WITH DATA PATH CIRCUITS FOR USE IN DOUBLE SENSE AMP ARCHITECTURE WITH FRACTIONAL BIT ASSIGNMENT IN NON-VOLATILE MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/511749 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19244330 [patent_doc_number] => 12014781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Memory device supporting interleaved operations and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/507326 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17734 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19014649 [patent_doc_number] => 11921578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Error correction methods and semiconductor devices and semiconductor systems using the error correction methods and the semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/504936 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 27503 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18312869 [patent_doc_number] => 20230116769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => METHOD FOR SELF-CALIBRATING TDQSCK THAT IS SKEW BETWEEN RISING EDGE OF MEMORY CLOCK SIGNAL AND RISING EDGE OF DQS SIGNAL DURING READ OPERATION AND ASSOCIATED SIGNAL PROCESSING CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/499870 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17917208 [patent_doc_number] => 20220319604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/495520 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18278380 [patent_doc_number] => 20230093852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR [patent_app_type] => utility [patent_app_number] => 17/448846 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18548028 [patent_doc_number] => 11721386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Sensing and tuning for memory die power management [patent_app_type] => utility [patent_app_number] => 17/470743 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18721253 [patent_doc_number] => 11798605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/470411 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18223173 [patent_doc_number] => 20230062167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WRITE REQUEST THRESHOLDING [patent_app_type] => utility [patent_app_number] => 17/412037 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17262918 [patent_doc_number] => 20210375903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 17/400598 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400598 [rel_patent_id] =>[rel_patent_doc_number] =>)