Search

Minh D. Dinh

Examiner (ID: 16802, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827
Total Applications
472
Issued Applications
435
Pending Applications
37
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17917208 [patent_doc_number] => 20220319604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/495520 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495520
Semiconductor memory device Oct 5, 2021 Issued
Array ( [id] => 18278380 [patent_doc_number] => 20230093852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR [patent_app_type] => utility [patent_app_number] => 17/448846 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448846
Pseudo-dual-port SRAM with burst-mode address comparator Sep 23, 2021 Issued
Array ( [id] => 18721253 [patent_doc_number] => 11798605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/470411 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470411
Memory system Sep 8, 2021 Issued
Array ( [id] => 18548028 [patent_doc_number] => 11721386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Sensing and tuning for memory die power management [patent_app_type] => utility [patent_app_number] => 17/470743 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470743
Sensing and tuning for memory die power management Sep 8, 2021 Issued
Array ( [id] => 18223173 [patent_doc_number] => 20230062167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WRITE REQUEST THRESHOLDING [patent_app_type] => utility [patent_app_number] => 17/412037 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412037
Write request thresholding Aug 24, 2021 Issued
Array ( [id] => 17262918 [patent_doc_number] => 20210375903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 17/400598 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400598
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells Aug 11, 2021 Issued
Array ( [id] => 18183147 [patent_doc_number] => 20230043877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => DYNAMIC READ-LEVEL THRESHOLDS IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/396386 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396386
Dynamic read-level thresholds in memory systems Aug 5, 2021 Issued
Array ( [id] => 18494568 [patent_doc_number] => 11699993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Signal sampling with offset calibration [patent_app_type] => utility [patent_app_number] => 17/395069 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14900 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395069
Signal sampling with offset calibration Aug 4, 2021 Issued
Array ( [id] => 18593142 [patent_doc_number] => 11742051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Sensor for performance variation of memory read and write characteristics [patent_app_type] => utility [patent_app_number] => 17/379906 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379906
Sensor for performance variation of memory read and write characteristics Jul 18, 2021 Issued
Array ( [id] => 18645489 [patent_doc_number] => 11769567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Devices and methods for preventing errors and detecting faults within a memory device [patent_app_type] => utility [patent_app_number] => 17/379213 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379213
Devices and methods for preventing errors and detecting faults within a memory device Jul 18, 2021 Issued
Array ( [id] => 17645052 [patent_doc_number] => 20220172791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => THRESHOLD SWITCH STRUCTURE AND MEMORY CELL ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/379168 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379168
Threshold switch structure and memory cell arrangement Jul 18, 2021 Issued
Array ( [id] => 18387071 [patent_doc_number] => 11657860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Memory package and storage device including the same [patent_app_type] => utility [patent_app_number] => 17/361780 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361780
Memory package and storage device including the same Jun 28, 2021 Issued
Array ( [id] => 17157654 [patent_doc_number] => 20210318705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT FOR MONITORING OUTPUT VOLTAGE, MEMORY MODULE INCLUDING POWER MANAGEMENT INTEGRATED CIRCUIT AND MEMORY DEVICE, AND OPERATING METHOD OF MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 17/358123 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358123
Power management integrated circuit for monitoring output voltage, memory module including power management integrated circuit and memory device, and operating method of memory module Jun 24, 2021 Issued
Array ( [id] => 17637901 [patent_doc_number] => 11348630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Self reference for ferroelectric memory [patent_app_type] => utility [patent_app_number] => 17/348229 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348229
Self reference for ferroelectric memory Jun 14, 2021 Issued
Array ( [id] => 17115320 [patent_doc_number] => 20210295917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => APPARATUSES AND METHODS FOR DECODING ADDRESSES FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/342116 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342116
Apparatuses and methods for decoding addresses for memory Jun 7, 2021 Issued
Array ( [id] => 18548022 [patent_doc_number] => 11721380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Word-line driver and method of operating a word-line driver [patent_app_type] => utility [patent_app_number] => 17/336626 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336626
Word-line driver and method of operating a word-line driver Jun 1, 2021 Issued
Array ( [id] => 17099957 [patent_doc_number] => 20210287748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => NAND TEMPERATURE DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/331395 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331395
NAND temperature data management May 25, 2021 Issued
Array ( [id] => 18131129 [patent_doc_number] => 11557344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Resistive random access memory device [patent_app_type] => utility [patent_app_number] => 17/330248 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330248
Resistive random access memory device May 24, 2021 Issued
Array ( [id] => 18317383 [patent_doc_number] => 11631467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Determining read voltages for memory systems [patent_app_type] => utility [patent_app_number] => 17/321933 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321933
Determining read voltages for memory systems May 16, 2021 Issued
Array ( [id] => 17992951 [patent_doc_number] => 20220358988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => VOLTAGE ADJUSTMENT OF MEMORY DIES BASED ON WEIGHTED FEEDBACK [patent_app_type] => utility [patent_app_number] => 17/315711 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315711
Voltage adjustment of memory dies based on weighted feedback May 9, 2021 Issued
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