Search

Minh D. Dinh

Examiner (ID: 15854, Phone: (571)270-5375 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2825
Total Applications
494
Issued Applications
460
Pending Applications
27
Abandoned Applications
14

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19079282 [patent_doc_number] => 11948657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Sense amplifier layout designs and related apparatuses and methods [patent_app_type] => utility [patent_app_number] => 17/547574 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12668 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547574
Sense amplifier layout designs and related apparatuses and methods Dec 9, 2021 Issued
Array ( [id] => 17509248 [patent_doc_number] => 20220102351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => APPARATUSES INCLUDING ELONGATE PILLARS OF ACCESS DEVICES [patent_app_type] => utility [patent_app_number] => 17/643316 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643316
Apparatuses including elongate pillars of access devices Dec 7, 2021 Issued
Array ( [id] => 18112669 [patent_doc_number] => 20230005549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/534210 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534210
Semiconductor memory device Nov 22, 2021 Issued
Array ( [id] => 18562748 [patent_doc_number] => 11727998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Memory system and memory control method [patent_app_type] => utility [patent_app_number] => 17/512394 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512394
Memory system and memory control method Oct 26, 2021 Issued
Array ( [id] => 18339168 [patent_doc_number] => 20230131117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DATA CONVERSION WITH DATA PATH CIRCUITS FOR USE IN DOUBLE SENSE AMP ARCHITECTURE WITH FRACTIONAL BIT ASSIGNMENT IN NON-VOLATILE MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/511749 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511749
Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures Oct 26, 2021 Issued
Array ( [id] => 19244330 [patent_doc_number] => 12014781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Memory device supporting interleaved operations and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/507326 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17734 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/507326
Memory device supporting interleaved operations and memory system including the same Oct 20, 2021 Issued
Array ( [id] => 19014649 [patent_doc_number] => 11921578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Error correction methods and semiconductor devices and semiconductor systems using the error correction methods and the semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/504936 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 27503 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504936
Error correction methods and semiconductor devices and semiconductor systems using the error correction methods and the semiconductor devices Oct 18, 2021 Issued
Array ( [id] => 18312869 [patent_doc_number] => 20230116769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => METHOD FOR SELF-CALIBRATING TDQSCK THAT IS SKEW BETWEEN RISING EDGE OF MEMORY CLOCK SIGNAL AND RISING EDGE OF DQS SIGNAL DURING READ OPERATION AND ASSOCIATED SIGNAL PROCESSING CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/499870 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499870
Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuit Oct 12, 2021 Issued
Array ( [id] => 17917208 [patent_doc_number] => 20220319604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/495520 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495520
Semiconductor memory device Oct 5, 2021 Issued
Array ( [id] => 18278380 [patent_doc_number] => 20230093852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR [patent_app_type] => utility [patent_app_number] => 17/448846 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448846
Pseudo-dual-port SRAM with burst-mode address comparator Sep 23, 2021 Issued
Array ( [id] => 18721253 [patent_doc_number] => 11798605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/470411 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470411
Memory system Sep 8, 2021 Issued
Array ( [id] => 18548028 [patent_doc_number] => 11721386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Sensing and tuning for memory die power management [patent_app_type] => utility [patent_app_number] => 17/470743 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470743
Sensing and tuning for memory die power management Sep 8, 2021 Issued
Array ( [id] => 18223173 [patent_doc_number] => 20230062167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WRITE REQUEST THRESHOLDING [patent_app_type] => utility [patent_app_number] => 17/412037 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412037
Write request thresholding Aug 24, 2021 Issued
Array ( [id] => 17262918 [patent_doc_number] => 20210375903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 17/400598 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400598
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells Aug 11, 2021 Issued
Array ( [id] => 18183147 [patent_doc_number] => 20230043877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => DYNAMIC READ-LEVEL THRESHOLDS IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/396386 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396386
Dynamic read-level thresholds in memory systems Aug 5, 2021 Issued
Array ( [id] => 18494568 [patent_doc_number] => 11699993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Signal sampling with offset calibration [patent_app_type] => utility [patent_app_number] => 17/395069 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14900 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395069
Signal sampling with offset calibration Aug 4, 2021 Issued
Array ( [id] => 18645489 [patent_doc_number] => 11769567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Devices and methods for preventing errors and detecting faults within a memory device [patent_app_type] => utility [patent_app_number] => 17/379213 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7633 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379213
Devices and methods for preventing errors and detecting faults within a memory device Jul 18, 2021 Issued
Array ( [id] => 17645052 [patent_doc_number] => 20220172791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => THRESHOLD SWITCH STRUCTURE AND MEMORY CELL ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/379168 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379168
Threshold switch structure and memory cell arrangement Jul 18, 2021 Issued
Array ( [id] => 18593142 [patent_doc_number] => 11742051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Sensor for performance variation of memory read and write characteristics [patent_app_type] => utility [patent_app_number] => 17/379906 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379906
Sensor for performance variation of memory read and write characteristics Jul 18, 2021 Issued
Array ( [id] => 18387071 [patent_doc_number] => 11657860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Memory package and storage device including the same [patent_app_type] => utility [patent_app_number] => 17/361780 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361780
Memory package and storage device including the same Jun 28, 2021 Issued
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