
Minh D. Dinh
Examiner (ID: 3390, Phone: (571)270-5375 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2825 |
| Total Applications | 480 |
| Issued Applications | 442 |
| Pending Applications | 36 |
| Abandoned Applications | 13 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18183147
[patent_doc_number] => 20230043877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => DYNAMIC READ-LEVEL THRESHOLDS IN MEMORY SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/396386
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396386
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396386 | Dynamic read-level thresholds in memory systems | Aug 5, 2021 | Issued |
Array
(
[id] => 18494568
[patent_doc_number] => 11699993
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Signal sampling with offset calibration
[patent_app_type] => utility
[patent_app_number] => 17/395069
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 14900
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395069
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/395069 | Signal sampling with offset calibration | Aug 4, 2021 | Issued |
Array
(
[id] => 18645489
[patent_doc_number] => 11769567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Devices and methods for preventing errors and detecting faults within a memory device
[patent_app_type] => utility
[patent_app_number] => 17/379213
[patent_app_country] => US
[patent_app_date] => 2021-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 7633
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379213
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/379213 | Devices and methods for preventing errors and detecting faults within a memory device | Jul 18, 2021 | Issued |
Array
(
[id] => 17645052
[patent_doc_number] => 20220172791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => THRESHOLD SWITCH STRUCTURE AND MEMORY CELL ARRANGEMENT
[patent_app_type] => utility
[patent_app_number] => 17/379168
[patent_app_country] => US
[patent_app_date] => 2021-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13492
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379168
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/379168 | Threshold switch structure and memory cell arrangement | Jul 18, 2021 | Issued |
Array
(
[id] => 18593142
[patent_doc_number] => 11742051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Sensor for performance variation of memory read and write characteristics
[patent_app_type] => utility
[patent_app_number] => 17/379906
[patent_app_country] => US
[patent_app_date] => 2021-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 16353
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379906
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/379906 | Sensor for performance variation of memory read and write characteristics | Jul 18, 2021 | Issued |
Array
(
[id] => 18387071
[patent_doc_number] => 11657860
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Memory package and storage device including the same
[patent_app_type] => utility
[patent_app_number] => 17/361780
[patent_app_country] => US
[patent_app_date] => 2021-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 15808
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361780
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/361780 | Memory package and storage device including the same | Jun 28, 2021 | Issued |
Array
(
[id] => 17157654
[patent_doc_number] => 20210318705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT FOR MONITORING OUTPUT VOLTAGE, MEMORY MODULE INCLUDING POWER MANAGEMENT INTEGRATED CIRCUIT AND MEMORY DEVICE, AND OPERATING METHOD OF MEMORY MODULE
[patent_app_type] => utility
[patent_app_number] => 17/358123
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13380
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358123
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/358123 | Power management integrated circuit for monitoring output voltage, memory module including power management integrated circuit and memory device, and operating method of memory module | Jun 24, 2021 | Issued |
Array
(
[id] => 17637901
[patent_doc_number] => 11348630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Self reference for ferroelectric memory
[patent_app_type] => utility
[patent_app_number] => 17/348229
[patent_app_country] => US
[patent_app_date] => 2021-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12256
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348229
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/348229 | Self reference for ferroelectric memory | Jun 14, 2021 | Issued |
Array
(
[id] => 17115320
[patent_doc_number] => 20210295917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => APPARATUSES AND METHODS FOR DECODING ADDRESSES FOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/342116
[patent_app_country] => US
[patent_app_date] => 2021-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5911
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342116
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342116 | Apparatuses and methods for decoding addresses for memory | Jun 7, 2021 | Issued |
Array
(
[id] => 18548022
[patent_doc_number] => 11721380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Word-line driver and method of operating a word-line driver
[patent_app_type] => utility
[patent_app_number] => 17/336626
[patent_app_country] => US
[patent_app_date] => 2021-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5465
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336626
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/336626 | Word-line driver and method of operating a word-line driver | Jun 1, 2021 | Issued |
Array
(
[id] => 17099957
[patent_doc_number] => 20210287748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => NAND TEMPERATURE DATA MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 17/331395
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13828
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/331395 | NAND temperature data management | May 25, 2021 | Issued |
Array
(
[id] => 18131129
[patent_doc_number] => 11557344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Resistive random access memory device
[patent_app_type] => utility
[patent_app_number] => 17/330248
[patent_app_country] => US
[patent_app_date] => 2021-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 11169
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/330248 | Resistive random access memory device | May 24, 2021 | Issued |
Array
(
[id] => 18317383
[patent_doc_number] => 11631467
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-18
[patent_title] => Determining read voltages for memory systems
[patent_app_type] => utility
[patent_app_number] => 17/321933
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 12541
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321933
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321933 | Determining read voltages for memory systems | May 16, 2021 | Issued |
Array
(
[id] => 17992951
[patent_doc_number] => 20220358988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => VOLTAGE ADJUSTMENT OF MEMORY DIES BASED ON WEIGHTED FEEDBACK
[patent_app_type] => utility
[patent_app_number] => 17/315711
[patent_app_country] => US
[patent_app_date] => 2021-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13245
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315711
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/315711 | Voltage adjustment of memory dies based on weighted feedback | May 9, 2021 | Issued |
Array
(
[id] => 17878334
[patent_doc_number] => 11450355
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-09-20
[patent_title] => Semiconductor memory with temperature dependence
[patent_app_type] => utility
[patent_app_number] => 17/306918
[patent_app_country] => US
[patent_app_date] => 2021-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5875
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306918
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/306918 | Semiconductor memory with temperature dependence | May 2, 2021 | Issued |
Array
(
[id] => 18234743
[patent_doc_number] => 11599301
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Semiconductor memory device and system including the same
[patent_app_type] => utility
[patent_app_number] => 17/245325
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 26
[patent_no_of_words] => 9947
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/245325 | Semiconductor memory device and system including the same | Apr 29, 2021 | Issued |
Array
(
[id] => 17565048
[patent_doc_number] => 20220129197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/244060
[patent_app_country] => US
[patent_app_date] => 2021-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12856
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244060
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/244060 | Memory device and memory system including the same | Apr 28, 2021 | Issued |
Array
(
[id] => 17011060
[patent_doc_number] => 20210242221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => Integrated Assemblies Having Ferroelectric Transistors with Heterostructure Active Regions
[patent_app_type] => utility
[patent_app_number] => 17/235848
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5655
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235848
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235848 | Integrated assemblies having ferroelectric transistors with heterostructure active regions | Apr 19, 2021 | Issued |
Array
(
[id] => 17431451
[patent_doc_number] => 20220059160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => Superconductive Memory Cells and Devices
[patent_app_type] => utility
[patent_app_number] => 17/234701
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234701
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/234701 | Superconductive memory cells and devices | Apr 18, 2021 | Issued |
Array
(
[id] => 18131143
[patent_doc_number] => 11557358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Memory apparatus and method of operation using adaptive erase time compensation for segmented erase
[patent_app_type] => utility
[patent_app_number] => 17/231071
[patent_app_country] => US
[patent_app_date] => 2021-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 31
[patent_no_of_words] => 13132
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231071
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/231071 | Memory apparatus and method of operation using adaptive erase time compensation for segmented erase | Apr 14, 2021 | Issued |