Minh N. Trinh

Array ( [id] => 19985765 [patent_doc_number] => 20250123987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SYSTEM AND METHOD FOR SUPPORTING MULTI-MODE AND/OR MULTI-SPEED NON-VOLATILE MEMORY (NVM) EXPRESS (NVMe) OVER FABRICS (NVMe-oF) DEVICES [patent_app_type] => utility [patent_app_number] => 18/990844 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000807 [patent_doc_number] => 20250139029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => OFF-MODULE DATA BUFFER [patent_app_type] => utility [patent_app_number] => 18/941090 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20018132 [patent_doc_number] => 20250156354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => INTELLIGENT MOVEMENT OF EXTERNAL CONTENT TO INTERNAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/933348 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18933348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19711366 [patent_doc_number] => 20250021508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => METHODS AND APPARATUS TO PREFORM INTER-INTEGRATED CIRCUIT ADDRESS MODIFICATION [patent_app_type] => utility [patent_app_number] => 18/896431 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19772099 [patent_doc_number] => 20250053525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => INPUT/OUTPUT EXPANDER REGISTER ADDRESSING [patent_app_type] => utility [patent_app_number] => 18/790156 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20474990 [patent_doc_number] => 20260017211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => COMPUTER SYSTEM AND MODE SWITCHING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/786554 [patent_app_country] => US [patent_app_date] => 2024-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19711363 [patent_doc_number] => 20250021505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => vRAN with PCIe Fronthaul [patent_app_type] => utility [patent_app_number] => 18/774601 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20395465 [patent_doc_number] => 20250370940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => HOST DEVICE AND DRIVING METHOD [patent_app_type] => utility [patent_app_number] => 18/767241 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20421923 [patent_doc_number] => 20250384008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => MULTI-INTERFACE/PROTOCOL COMPONENT MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 18/744982 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19725904 [patent_doc_number] => 20250028655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => PUSH METHOD FOR PERIPHERAL DEVICE REDIRECTION [patent_app_type] => utility [patent_app_number] => 18/745310 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20323295 [patent_doc_number] => 20250335383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => FIBRE CHANNEL PROTOCOL EXCHANGE HANDLING [patent_app_type] => utility [patent_app_number] => 18/646206 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20500731 [patent_doc_number] => 20260030192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => Circuit Board of Graphics Processing Unit and Server System [patent_app_type] => utility [patent_app_number] => 19/139143 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19139143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20290149 [patent_doc_number] => 20250315392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => DYNAMICALLY ROUTING INPUT/OUTPUT COMMANDS [patent_app_type] => utility [patent_app_number] => 18/630208 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19482189 [patent_doc_number] => 20240330231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 18/616411 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20249898 [patent_doc_number] => 20250298767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SYSTEMS AND METHODS FOR SELECTING AN OPTIMAL COMMUNICATION PATH IN A HETEROGENEOUS COMPUTING PLATFORM [patent_app_type] => utility [patent_app_number] => 18/611765 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20208652 [patent_doc_number] => 20250278372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => ACCESSING A SECONDARY SHARED RESOURCE USING VIRTUAL IDENTIFIERS [patent_app_type] => utility [patent_app_number] => 18/591498 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514296 [patent_doc_number] => 20240345982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => PARALLEL RAS CHANNELS IN CXL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/444550 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20160006 [patent_doc_number] => 12386634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Systems and methods for distributed control [patent_app_type] => utility [patent_app_number] => 18/440850 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20101773 [patent_doc_number] => 20250231709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => QUALITY OF SERVICE POLICY SETS [patent_app_type] => utility [patent_app_number] => 18/412912 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20101958 [patent_doc_number] => 20250231894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => INPUT/OUTPUT DEVICE IN A HIGH DENSITY OR RACKMOUNT ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/412908 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412908 [rel_patent_id] =>[rel_patent_doc_number] =>)