| Application number | Title of the application | Filing Date | Status |
|---|
| 95/000092 | AUTONOMOUS, SELF LEVELING, SELF CORRECTING STABILIZED PLATFORM | May 4, 2005 | Issued |
| 90/007493 | COMPOSITE FILTER, ANTENNA DUPLEXER, AND COMMUNICATION APPARATUS | Apr 3, 2005 | Pending |
Array
(
[id] => 10191290
[patent_doc_number] => RE045828
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2015-12-29
[patent_title] => 'Method for determining a printer\'s signature and the number of dots per inch printed in a document to provide proof that the printer printed a particular document'
[patent_app_type] => reissue
[patent_app_number] => 11/084869
[patent_app_country] => US
[patent_app_date] => 2005-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3661
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11084869
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/084869 | Method for determining a printer's signature and the number of dots per inch printed in a document to provide proof that the printer printed a particular document | Mar 16, 2005 | Issued |
| 90/007395 | SUPER RADIANT LIGHT SOURCE | Jan 26, 2005 | Issued |
| 90/007392 | STRUCTURES AND METHODS FOR ENHANCING CAPACITORS IN INTEGRATED CIRCUITS | Jan 24, 2005 | Issued |
| 90/007383 | METHOD FOR REDUCING TENSILE STRESS ZONES IN THE SURFACE OF A PART | Jan 17, 2005 | Issued |
Array
(
[id] => 7095528
[patent_doc_number] => 20050127986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Squaring cells and multipliers using summed exponentials'
[patent_app_type] => utility
[patent_app_number] => 11/032993
[patent_app_country] => US
[patent_app_date] => 2005-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10183
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127986.pdf
[firstpage_image] =>[orig_patent_app_number] => 11032993
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/032993 | Squaring cells and multipliers using summed exponentials | Jan 9, 2005 | Abandoned |
| 90/007356 | MEASURING POSITIONS OF COPLANARITY OF CONTRACT ELEMENTS OF AN ELECTRONIC COMPONENT WITH A FLAT ILLUMINATION AND TWO CAMERAS | Dec 21, 2004 | Issued |
Array
(
[id] => 775112
[patent_doc_number] => 07002386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Self-limiting pulse width modulation regulator'
[patent_app_type] => utility
[patent_app_number] => 11/022098
[patent_app_country] => US
[patent_app_date] => 2004-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3450
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/002/07002386.pdf
[firstpage_image] =>[orig_patent_app_number] => 11022098
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022098 | Self-limiting pulse width modulation regulator | Dec 21, 2004 | Issued |
Array
(
[id] => 7101919
[patent_doc_number] => 20050104645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations'
[patent_app_type] => utility
[patent_app_number] => 11/014647
[patent_app_country] => US
[patent_app_date] => 2004-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3019
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20050104645.pdf
[firstpage_image] =>[orig_patent_app_number] => 11014647
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/014647 | Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations | Dec 15, 2004 | Abandoned |
Array
(
[id] => 7621968
[patent_doc_number] => 06977533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => '32V H-bridge driver with CMOS circuits'
[patent_app_type] => utility
[patent_app_number] => 11/010735
[patent_app_country] => US
[patent_app_date] => 2004-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4064
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977533.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010735 | 32V H-bridge driver with CMOS circuits | Dec 12, 2004 | Issued |
| 90/007336 | REFLECTIVE, OPTICAL RECORD CARRIER | Dec 7, 2004 | Issued |
| 95/000060 | HIGH INTENSITY DISCHARGE (HID) LAMP WITH INTEGRAL BALLAST AND UNDERWATER LIGHTING SYSTEMS INCORPORATING SAME | Nov 14, 2004 | Issued |
Array
(
[id] => 7155633
[patent_doc_number] => 20050083138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'PLL circuit'
[patent_app_type] => utility
[patent_app_number] => 10/963718
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6361
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20050083138.pdf
[firstpage_image] =>[orig_patent_app_number] => 10963718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/963718 | PLL circuit with simulation components to reduce phase offset | Oct 13, 2004 | Issued |
Array
(
[id] => 7081075
[patent_doc_number] => 20050046455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'DLL circuit'
[patent_app_type] => utility
[patent_app_number] => 10/964244
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5515
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20050046455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10964244
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/964244 | DLL circuit capable of preventing malfunctioning causing locking in an antiphase state | Oct 11, 2004 | Issued |
Array
(
[id] => 7155583
[patent_doc_number] => 20050083103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Controlling signal states and leakage current during a sleep mode'
[patent_app_type] => utility
[patent_app_number] => 10/960035
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3731
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20050083103.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960035 | Controlling signal states and leakage current during a sleep mode | Oct 6, 2004 | Abandoned |
| 90/007227 | ELECTRONIC POWER METER | Sep 26, 2004 | Issued |
| 95/000052 | CIRCUITS AND TECHNIQUES FOR CAPACITOR CHARGING CIRCUITS | Sep 22, 2004 | Issued |
| 95/000051 | CIRCUITS AND TECHNIQUES FOR CAPACITOR CHARGING CIRCUITS | Sep 22, 2004 | Issued |
Array
(
[id] => 6970090
[patent_doc_number] => 20050035800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Percent-of-clock delay circuits with enhanced phase jitter immunity'
[patent_app_type] => utility
[patent_app_number] => 10/945588
[patent_app_country] => US
[patent_app_date] => 2004-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5280
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20050035800.pdf
[firstpage_image] =>[orig_patent_app_number] => 10945588
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/945588 | Percent-of-clock delay circuits with enhanced phase jitter immunity | Sep 20, 2004 | Issued |
