Minh T. Nguyen

Array ( [id] => 760060 [patent_doc_number] => 07015735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Semiconductor integrated circuit having built-in PLL circuit' [patent_app_type] => utility [patent_app_number] => 10/739117 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9694 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015735.pdf [firstpage_image] =>[orig_patent_app_number] => 10739117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6994546 [patent_doc_number] => 20050134324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Variable threshold comparator interface circuit' [patent_app_type] => utility [patent_app_number] => 10/740333 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134324.pdf [firstpage_image] =>[orig_patent_app_number] => 10740333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7414545 [patent_doc_number] => 20040207451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Impedance trimming circuit' [patent_app_type] => new [patent_app_number] => 10/723101 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11270 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207451.pdf [firstpage_image] =>[orig_patent_app_number] => 10723101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 997027 [patent_doc_number] => 06914460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Counter-based clock doubler circuits and methods' [patent_app_type] => utility [patent_app_number] => 10/719830 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 11039 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914460.pdf [firstpage_image] =>[orig_patent_app_number] => 10719830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 785963 [patent_doc_number] => 06989696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'System and method for synchronizing divide-by counters' [patent_app_type] => utility [patent_app_number] => 10/707066 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3603 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989696.pdf [firstpage_image] =>[orig_patent_app_number] => 10707066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 793535 [patent_doc_number] => 06982581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Duty cycle correction circuit' [patent_app_type] => utility [patent_app_number] => 10/713162 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4485 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982581.pdf [firstpage_image] =>[orig_patent_app_number] => 10713162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 954222 [patent_doc_number] => 06958637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Spark current cancellation in charge pump of high speed phase lock loop circuit' [patent_app_type] => utility [patent_app_number] => 10/605982 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2316 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958637.pdf [firstpage_image] =>[orig_patent_app_number] => 10605982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7319423 [patent_doc_number] => 20040135612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Delayed tap signal generating circuit for controlling delay by interpolating two input clocks' [patent_app_type] => new [patent_app_number] => 10/698383 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135612.pdf [firstpage_image] =>[orig_patent_app_number] => 10698383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 726375 [patent_doc_number] => 07046057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-16 [patent_title] => 'System and method for synchronizing devices' [patent_app_type] => utility [patent_app_number] => 10/699906 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5839 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046057.pdf [firstpage_image] =>[orig_patent_app_number] => 10699906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7604772 [patent_doc_number] => 07116159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method and apparatus for adjusting an active filter' [patent_app_type] => utility [patent_app_number] => 10/697418 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2408 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116159.pdf [firstpage_image] =>[orig_patent_app_number] => 10697418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 985950 [patent_doc_number] => 06924684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-02 [patent_title] => 'Counter-based phase shifter circuits and methods with optional duty cycle correction' [patent_app_type] => utility [patent_app_number] => 10/696227 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7330 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924684.pdf [firstpage_image] =>[orig_patent_app_number] => 10696227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1006412 [patent_doc_number] => 06906571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Counter-based phased clock generator circuits and methods' [patent_app_type] => utility [patent_app_number] => 10/696226 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10532 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906571.pdf [firstpage_image] =>[orig_patent_app_number] => 10696226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 735120 [patent_doc_number] => 07038509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method and system for providing a phase-locked loop with reduced spurious tones' [patent_app_type] => utility [patent_app_number] => 10/694450 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038509.pdf [firstpage_image] =>[orig_patent_app_number] => 10694450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 997020 [patent_doc_number] => 06914458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Method and device for generating a signal with a frequency equal to the product of a reference frequency and a real number' [patent_app_type] => utility [patent_app_number] => 10/688208 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3316 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914458.pdf [firstpage_image] =>[orig_patent_app_number] => 10688208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7355633 [patent_doc_number] => 20040090273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Digital adjustable chip oscillator' [patent_app_type] => new [patent_app_number] => 10/688516 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 7289 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090273.pdf [firstpage_image] =>[orig_patent_app_number] => 10688516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7373521 [patent_doc_number] => 20040080349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Clock signal generation circuit' [patent_app_type] => new [patent_app_number] => 10/684449 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6444 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080349.pdf [firstpage_image] =>[orig_patent_app_number] => 10684449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944466 [patent_doc_number] => 06967520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Gate drive circuit, which makes the gate-charge flow back to the load and the main power source' [patent_app_type] => utility [patent_app_number] => 10/683588 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5076 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967520.pdf [firstpage_image] =>[orig_patent_app_number] => 10683588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7222547 [patent_doc_number] => 20050077936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Circuit and method for reducing jitter in a PLL of high speed serial links' [patent_app_type] => utility [patent_app_number] => 10/685022 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1687 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077936.pdf [firstpage_image] =>[orig_patent_app_number] => 10685022 [rel_patent_id] =>[rel_patent_doc_number] =>)