
Minh T. Nguyen
Examiner (ID: 11202)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3991, 2816, 3992 |
| Total Applications | 873 |
| Issued Applications | 770 |
| Pending Applications | 36 |
| Abandoned Applications | 71 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 779950
[patent_doc_number] => 06995596
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-07
[patent_title] => 'Process and skew tolerant precharge circuit'
[patent_app_type] => utility
[patent_app_number] => 10/685657
[patent_app_country] => US
[patent_app_date] => 2003-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3629
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/995/06995596.pdf
[firstpage_image] =>[orig_patent_app_number] => 10685657
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/685657 | Process and skew tolerant precharge circuit | Oct 13, 2003 | Issued |
Array
(
[id] => 969054
[patent_doc_number] => 06940332
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Level shift circuit having control circuits for high speed, area saving and power saving'
[patent_app_type] => utility
[patent_app_number] => 10/681370
[patent_app_country] => US
[patent_app_date] => 2003-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13466
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/940/06940332.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681370 | Level shift circuit having control circuits for high speed, area saving and power saving | Oct 8, 2003 | Issued |
Array
(
[id] => 7244004
[patent_doc_number] => 20050073347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'PHASE SHIFTER CONTROL VOLTAGE DISTRIBUTION IN A PHASED ARRAY UTILIZING VOLTAGE-PROPORTIONAL PHASE SHIFT DEVICES'
[patent_app_type] => utility
[patent_app_number] => 10/679608
[patent_app_country] => US
[patent_app_date] => 2003-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1904
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073347.pdf
[firstpage_image] =>[orig_patent_app_number] => 10679608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/679608 | Phase shifter control voltage distribution in a phased array utilizing voltage-proportional phase shift devices | Oct 5, 2003 | Issued |
Array
(
[id] => 7244032
[patent_doc_number] => 20050073351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Switched-capacitor sample/hold having reduced amplifier slew-rate and settling time requirements'
[patent_app_type] => utility
[patent_app_number] => 10/677449
[patent_app_country] => US
[patent_app_date] => 2003-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3012
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073351.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677449
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677449 | Switched-capacitor sample/hold having reduced amplifier slew-rate and settling time requirements | Oct 1, 2003 | Issued |
Array
(
[id] => 941638
[patent_doc_number] => 06970030
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-29
[patent_title] => 'Dual phased-locked loop structure having configurable intermediate frequency and reduced susceptibility to interference'
[patent_app_type] => utility
[patent_app_number] => 10/676626
[patent_app_country] => US
[patent_app_date] => 2003-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5672
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/970/06970030.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676626
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676626 | Dual phased-locked loop structure having configurable intermediate frequency and reduced susceptibility to interference | Sep 30, 2003 | Issued |
Array
(
[id] => 7268209
[patent_doc_number] => 20040056727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Vibrating reed, vibrator, oscillator, and electronic device'
[patent_app_type] => new
[patent_app_number] => 10/672597
[patent_app_country] => US
[patent_app_date] => 2003-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5613
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20040056727.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672597
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672597 | Vibrating reed, vibrator, oscillator, and electronic device | Sep 25, 2003 | Issued |
Array
(
[id] => 7144647
[patent_doc_number] => 20040169530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'Method and apparatus for robust biasing of bipolar and BiCMOS differential architectures'
[patent_app_type] => new
[patent_app_number] => 10/672061
[patent_app_country] => US
[patent_app_date] => 2003-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6037
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20040169530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672061
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672061 | Method and apparatus for robust biasing of bipolar and BiCMOS differential architectures | Sep 25, 2003 | Abandoned |
Array
(
[id] => 1090492
[patent_doc_number] => 06828832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-07
[patent_title] => 'Voltage to current converter circuit'
[patent_app_type] => B2
[patent_app_number] => 10/605361
[patent_app_country] => US
[patent_app_date] => 2003-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2849
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/828/06828832.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605361
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605361 | Voltage to current converter circuit | Sep 24, 2003 | Issued |
Array
(
[id] => 938784
[patent_doc_number] => 06972613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-06
[patent_title] => 'Fuse latch circuit with non-disruptive re-interrogation'
[patent_app_type] => utility
[patent_app_number] => 10/657362
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3590
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/972/06972613.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657362
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657362 | Fuse latch circuit with non-disruptive re-interrogation | Sep 7, 2003 | Issued |
Array
(
[id] => 7286974
[patent_doc_number] => 20040108882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Fuse circuit and display driver circuit'
[patent_app_type] => new
[patent_app_number] => 10/657803
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6726
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20040108882.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657803
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657803 | Fuse circuit and display driver circuit | Sep 7, 2003 | Issued |
Array
(
[id] => 7178173
[patent_doc_number] => 20040201935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Driving circuit for semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/652072
[patent_app_country] => US
[patent_app_date] => 2003-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4695
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20040201935.pdf
[firstpage_image] =>[orig_patent_app_number] => 10652072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652072 | Overcurrent protection and masking circuitry for protection against an overcurrent condition | Sep 1, 2003 | Issued |
Array
(
[id] => 1054214
[patent_doc_number] => 06859113
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-22
[patent_title] => 'Temperature compensation mechanism for a micromechanical ring resonator'
[patent_app_type] => utility
[patent_app_number] => 10/650811
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 6177
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/859/06859113.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650811 | Temperature compensation mechanism for a micromechanical ring resonator | Aug 28, 2003 | Issued |
Array
(
[id] => 1006389
[patent_doc_number] => 06906562
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-14
[patent_title] => 'Counter-based clock multiplier circuits and methods'
[patent_app_type] => utility
[patent_app_number] => 10/651811
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 28
[patent_no_of_words] => 14456
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/906/06906562.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651811 | Counter-based clock multiplier circuits and methods | Aug 28, 2003 | Issued |
Array
(
[id] => 790996
[patent_doc_number] => 06985021
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-01-10
[patent_title] => 'Circuits and techniques for conditioning differential signals'
[patent_app_type] => utility
[patent_app_number] => 10/652521
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 5284
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/985/06985021.pdf
[firstpage_image] =>[orig_patent_app_number] => 10652521
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652521 | Circuits and techniques for conditioning differential signals | Aug 28, 2003 | Issued |
Array
(
[id] => 1151980
[patent_doc_number] => 06774700
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-10
[patent_title] => 'Current-mode logic differential signal generation circuit employing squelch'
[patent_app_type] => B1
[patent_app_number] => 10/651675
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3094
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/774/06774700.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651675
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651675 | Current-mode logic differential signal generation circuit employing squelch | Aug 28, 2003 | Issued |
Array
(
[id] => 1015396
[patent_doc_number] => 06894576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'Temperature compensation mechanism for a micromechanical ring resonator'
[patent_app_type] => utility
[patent_app_number] => 10/650685
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 6118
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/894/06894576.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650685
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650685 | Temperature compensation mechanism for a micromechanical ring resonator | Aug 28, 2003 | Issued |
Array
(
[id] => 1098063
[patent_doc_number] => 06822500
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Methods and apparatus for operating master-slave latches'
[patent_app_type] => B1
[patent_app_number] => 10/651176
[patent_app_country] => US
[patent_app_date] => 2003-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5647
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/822/06822500.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651176
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651176 | Methods and apparatus for operating master-slave latches | Aug 27, 2003 | Issued |
Array
(
[id] => 7621962
[patent_doc_number] => 06977539
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-20
[patent_title] => 'Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews'
[patent_app_type] => utility
[patent_app_number] => 10/648090
[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4694
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977539.pdf
[firstpage_image] =>[orig_patent_app_number] => 10648090
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/648090 | Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews | Aug 25, 2003 | Issued |
Array
(
[id] => 1054153
[patent_doc_number] => 06859081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-22
[patent_title] => 'Duty cycle correction circuit and delay locked loop having the same'
[patent_app_type] => utility
[patent_app_number] => 10/638994
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2771
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/859/06859081.pdf
[firstpage_image] =>[orig_patent_app_number] => 10638994
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/638994 | Duty cycle correction circuit and delay locked loop having the same | Aug 10, 2003 | Issued |
Array
(
[id] => 783730
[patent_doc_number] => 06992517
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'Self-limiting pulse width modulation regulator'
[patent_app_type] => utility
[patent_app_number] => 10/639078
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3476
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/992/06992517.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639078
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639078 | Self-limiting pulse width modulation regulator | Aug 10, 2003 | Issued |