
Miranda Le
Examiner (ID: 3965, Phone: (571)272-4112 , Office: P/2153 )
| Most Active Art Unit | 2153 |
| Art Unit(s) | 2167, 2169, 2177, 2159, 2168, 2153 |
| Total Applications | 680 |
| Issued Applications | 453 |
| Pending Applications | 48 |
| Abandoned Applications | 187 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17326477
[patent_doc_number] => 11217502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Semiconductor device packages and methods of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/676284
[patent_app_country] => US
[patent_app_date] => 2019-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4241
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676284
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/676284 | Semiconductor device packages and methods of manufacturing the same | Nov 5, 2019 | Issued |
Array
(
[id] => 17529965
[patent_doc_number] => 11302665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Power semiconductor apparatus and fabrication method for the same
[patent_app_type] => utility
[patent_app_number] => 16/676011
[patent_app_country] => US
[patent_app_date] => 2019-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 70
[patent_figures_cnt] => 127
[patent_no_of_words] => 35945
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676011
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/676011 | Power semiconductor apparatus and fabrication method for the same | Nov 5, 2019 | Issued |
Array
(
[id] => 18891047
[patent_doc_number] => 11869824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Thermal interface structures for integrated circuit packages
[patent_app_type] => utility
[patent_app_number] => 16/672858
[patent_app_country] => US
[patent_app_date] => 2019-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7697
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672858
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/672858 | Thermal interface structures for integrated circuit packages | Nov 3, 2019 | Issued |
Array
(
[id] => 15564599
[patent_doc_number] => 20200066711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => INTEGRATING A JUNCTION FIELD EFFECT TRANSISTOR INTO A VERTICAL FIELD EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 16/665083
[patent_app_country] => US
[patent_app_date] => 2019-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6787
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665083
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/665083 | Integrating a junction field effect transistor into a vertical field effect transistor | Oct 27, 2019 | Issued |
Array
(
[id] => 15807331
[patent_doc_number] => 20200126808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS THAT MANAGE HEAT TREATMENT OF DUMMY WAFER
[patent_app_type] => utility
[patent_app_number] => 16/655665
[patent_app_country] => US
[patent_app_date] => 2019-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15455
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655665
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/655665 | Heat treatment method and heat treatment apparatus that manage heat treatment of dummy wafer | Oct 16, 2019 | Issued |
Array
(
[id] => 15808015
[patent_doc_number] => 20200127150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => STRUCTURES AND METHODS FOR FORMING ELECTRODES OF SOLAR CELLS
[patent_app_type] => utility
[patent_app_number] => 16/653492
[patent_app_country] => US
[patent_app_date] => 2019-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4215
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653492
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/653492 | Structures and methods for forming electrodes of solar cells | Oct 14, 2019 | Issued |
Array
(
[id] => 17604189
[patent_doc_number] => 11332661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-17
[patent_title] => Modified perovskite quantum dot material, fabricating method thereof, and display device
[patent_app_type] => utility
[patent_app_number] => 16/630443
[patent_app_country] => US
[patent_app_date] => 2019-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2294
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630443
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/630443 | Modified perovskite quantum dot material, fabricating method thereof, and display device | Oct 11, 2019 | Issued |
Array
(
[id] => 17848190
[patent_doc_number] => 11437577
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-06
[patent_title] => Organic light emitting diode display device and method of fabricating same
[patent_app_type] => utility
[patent_app_number] => 16/615838
[patent_app_country] => US
[patent_app_date] => 2019-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2843
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16615838
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/615838 | Organic light emitting diode display device and method of fabricating same | Oct 10, 2019 | Issued |
Array
(
[id] => 18798669
[patent_doc_number] => 11832537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Titanium silicon nitride barrier layer
[patent_app_type] => utility
[patent_app_number] => 16/595912
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 10654
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595912
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/595912 | Titanium silicon nitride barrier layer | Oct 7, 2019 | Issued |
Array
(
[id] => 15530347
[patent_doc_number] => 20200057479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-20
[patent_title] => CHIP TRANSIENT TEMPERATURE PREDICTOR
[patent_app_type] => utility
[patent_app_number] => 16/595584
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7848
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595584
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/595584 | Chip transient temperature predictor | Oct 7, 2019 | Issued |
Array
(
[id] => 15369649
[patent_doc_number] => 20200020589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-16
[patent_title] => METHOD FOR FABRICATING A ROW OF MOS TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 16/582576
[patent_app_country] => US
[patent_app_date] => 2019-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4710
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582576
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/582576 | Method for fabricating a row of MOS transistors | Sep 24, 2019 | Issued |
Array
(
[id] => 17107592
[patent_doc_number] => 11127819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-21
[patent_title] => Gate all around transistors for different applications
[patent_app_type] => utility
[patent_app_number] => 16/571264
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8005
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571264
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571264 | Gate all around transistors for different applications | Sep 15, 2019 | Issued |
Array
(
[id] => 17381082
[patent_doc_number] => 11239114
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-01
[patent_title] => Semiconductor device with reduced contact resistance and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/571358
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 28
[patent_no_of_words] => 11143
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571358
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571358 | Semiconductor device with reduced contact resistance and methods of forming the same | Sep 15, 2019 | Issued |
Array
(
[id] => 16865986
[patent_doc_number] => 11024739
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Fin field effect transistor including a single diffusion break with a multi-layer dummy gate
[patent_app_type] => utility
[patent_app_number] => 16/570701
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 48
[patent_no_of_words] => 4466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/570701 | Fin field effect transistor including a single diffusion break with a multi-layer dummy gate | Sep 12, 2019 | Issued |
Array
(
[id] => 17018514
[patent_doc_number] => 11088160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Vertical semiconductor device and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 16/570089
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 51
[patent_no_of_words] => 24252
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570089
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/570089 | Vertical semiconductor device and fabrication method thereof | Sep 12, 2019 | Issued |
Array
(
[id] => 15905781
[patent_doc_number] => 20200152411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => METHOD OF ION IMPLANTATION AND AN APPARATUS FOR THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/566876
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8386
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566876
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566876 | Method of ion implantation and an apparatus for the same | Sep 10, 2019 | Issued |
Array
(
[id] => 16645654
[patent_doc_number] => 10923522
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Backside illuminated image sensor and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/565937
[patent_app_country] => US
[patent_app_date] => 2019-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5958
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565937
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/565937 | Backside illuminated image sensor and method of manufacturing the same | Sep 9, 2019 | Issued |
Array
(
[id] => 16521557
[patent_doc_number] => 10872782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-22
[patent_title] => Method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/561909
[patent_app_country] => US
[patent_app_date] => 2019-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561909
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/561909 | Method of manufacturing semiconductor device | Sep 4, 2019 | Issued |
Array
(
[id] => 17032932
[patent_doc_number] => 11094752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Display panel and preparation method thereof
[patent_app_type] => utility
[patent_app_number] => 16/612399
[patent_app_country] => US
[patent_app_date] => 2019-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2432
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16612399
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/612399 | Display panel and preparation method thereof | Aug 28, 2019 | Issued |
Array
(
[id] => 15687943
[patent_doc_number] => 20200098635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => METHOD OF CUTTING SUBSTRATE AND METHOD OF SINGULATING SEMICONDUCTOR CHIPS
[patent_app_type] => utility
[patent_app_number] => 16/539980
[patent_app_country] => US
[patent_app_date] => 2019-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7566
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539980
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/539980 | Method of cutting substrate and method of singulating semiconductor chips | Aug 12, 2019 | Issued |