Search

Misook Yu

Supervisory Patent Examiner (ID: 19361, Phone: (571)272-0839 , Office: P/1642 )

Most Active Art Unit
1642
Art Unit(s)
1642, 1641
Total Applications
872
Issued Applications
267
Pending Applications
201
Abandoned Applications
406

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20500455 [patent_doc_number] => 20260029915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => Dual-Port Interposer For Storage Drives [patent_app_type] => utility [patent_app_number] => 18/785255 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785255
Dual-Port Interposer For Storage Drives Jul 25, 2024 Pending
Array ( [id] => 20745709 [patent_doc_number] => 12645621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Presentation of direct accessed storage under a logical drive model [patent_app_type] => utility [patent_app_number] => 18/779904 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779904
Presentation of direct accessed storage under a logical drive model Jul 21, 2024 Issued
Array ( [id] => 20181245 [patent_doc_number] => 20250265203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY DEVICE AND COMPUTING SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/776498 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776498
Memory device and computing system including memory device Jul 17, 2024 Issued
Array ( [id] => 20487505 [patent_doc_number] => 20260023704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => Tunneling of Peripheral-Bus Protocol Traffic over Coherent Fabric and Chip-to-Chip or Die-to-Die Bus [patent_app_type] => utility [patent_app_number] => 18/773681 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773681
Tunneling of Peripheral-Bus Protocol Traffic over Coherent Fabric and Chip-to-Chip or Die-to-Die Bus Jul 15, 2024 Pending
Array ( [id] => 20117264 [patent_doc_number] => 12366967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Data masking for pulse amplitude modulation [patent_app_type] => utility [patent_app_number] => 18/768944 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768944
Data masking for pulse amplitude modulation Jul 9, 2024 Issued
Array ( [id] => 19759056 [patent_doc_number] => 20250047621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => OPTIMALLY BALANCED NETWORK SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/747118 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747118
OPTIMALLY BALANCED NETWORK SYSTEMS Jun 17, 2024 Pending
Array ( [id] => 19466510 [patent_doc_number] => 20240320180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => NON-VOLATILE THREE-DIMENSIONAL MEMORY CELL, STORAGE METHOD, AND CHIP ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/731414 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731414
NON-VOLATILE THREE-DIMENSIONAL MEMORY CELL, STORAGE METHOD, AND CHIP ASSEMBLY Jun 2, 2024 Pending
Array ( [id] => 20397396 [patent_doc_number] => 20250372871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => INFORMATION HANDLING SYSTEM DONGLE WITH EMBEDDED SEPARABLE ANTENNA [patent_app_type] => utility [patent_app_number] => 18/676757 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676757 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676757
INFORMATION HANDLING SYSTEM DONGLE WITH EMBEDDED SEPARABLE ANTENNA May 28, 2024 Pending
Array ( [id] => 19451195 [patent_doc_number] => 20240311325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => INTERFACE COMPONENT FOR DISTRIBUTED COMPONENTS OF A MACHINE LEARNING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/675103 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -42 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675103
INTERFACE COMPONENT FOR DISTRIBUTED COMPONENTS OF A MACHINE LEARNING SYSTEM May 26, 2024 Pending
Array ( [id] => 20745701 [patent_doc_number] => 12645613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Memory extension device, operation method of memory extension device, and computer readable storage medium for executing operation method [patent_app_type] => utility [patent_app_number] => 18/654767 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654767
Memory extension device, operation method of memory extension device, and computer readable storage medium for executing operation method May 2, 2024 Issued
Array ( [id] => 19383180 [patent_doc_number] => 20240273050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => NETWORK STORAGE METHOD, STORAGE SYSTEM, DATA PROCESSING UNIT, AND COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 18/647189 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647189
Network storage method, storage system, data processing unit, and computer system Apr 25, 2024 Issued
Array ( [id] => 20310856 [patent_doc_number] => 20250328485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Network-on-Chip Communication Method and Network-on-Chip Communication System Capable of Performing Communications for Different Networks [patent_app_type] => utility [patent_app_number] => 18/641444 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641444
Network-on-Chip Communication Method and Network-on-Chip Communication System Capable of Performing Communications for Different Networks Apr 21, 2024 Pending
Array ( [id] => 20257681 [patent_doc_number] => 12430031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Computing device with independently coherent nodes [patent_app_type] => utility [patent_app_number] => 18/641779 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641779
Computing device with independently coherent nodes Apr 21, 2024 Issued
Array ( [id] => 19802654 [patent_doc_number] => 20250068579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 18/640848 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640848
SYSTEM ON CHIP Apr 18, 2024 Pending
Array ( [id] => 20440227 [patent_doc_number] => 12511063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Host recovery for a stuck condition [patent_app_type] => utility [patent_app_number] => 18/638471 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638471
Host recovery for a stuck condition Apr 16, 2024 Issued
Array ( [id] => 20145682 [patent_doc_number] => 12380025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Storage circuit, chip, data processing method, and electronic device [patent_app_type] => utility [patent_app_number] => 18/633411 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633411 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633411
Storage circuit, chip, data processing method, and electronic device Apr 10, 2024 Issued
Array ( [id] => 19645102 [patent_doc_number] => 20240419622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CONNECTION DEVICE [patent_app_type] => utility [patent_app_number] => 18/612907 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612907
Connection device Mar 20, 2024 Issued
Array ( [id] => 19283951 [patent_doc_number] => 20240220427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC [patent_app_type] => utility [patent_app_number] => 18/605301 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605301
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC Mar 13, 2024 Issued
Array ( [id] => 19220428 [patent_doc_number] => 20240185132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DATA PATH FOR GPU MACHINE LEARNING TRAINING WITH KEY VALUE SSD [patent_app_type] => utility [patent_app_number] => 18/437769 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437769
Data path for GPU machine learning training with key value SSD Feb 8, 2024 Issued
Array ( [id] => 20152225 [patent_doc_number] => 20250252063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SYSTEM AND METHOD FOR DETERMINING PERIPHERAL DEVICE CONFIGURATIONS ACROSS A PLURALITY OF WORKSPACES FOR SEAMLESS USER PERIPHERAL DEVICE WORKSPACE ECOSYSTEM EXPERIENCE [patent_app_type] => utility [patent_app_number] => 18/430712 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430712
System and method for determining peripheral device configurations across a plurality of workspaces for seamless user peripheral device workspace ecosystem experience Feb 1, 2024 Issued
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