Search

Mitchell Hill

Examiner (ID: 19564)

Most Active Art Unit
3106
Art Unit(s)
3106, 2899
Total Applications
1496
Issued Applications
1329
Pending Applications
6
Abandoned Applications
161

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4366003 [patent_doc_number] => 06286069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Device which uses NOP command to share memory bus' [patent_app_type] => 1 [patent_app_number] => 9/270029 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1700 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286069.pdf [firstpage_image] =>[orig_patent_app_number] => 270029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270029
Device which uses NOP command to share memory bus Mar 15, 1999 Issued
Array ( [id] => 4388922 [patent_doc_number] => 06275949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Power controller for a peripheral device that stores the on/off state thereof when power is removed from the device' [patent_app_type] => 1 [patent_app_number] => 9/267677 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3594 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275949.pdf [firstpage_image] =>[orig_patent_app_number] => 267677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267677
Power controller for a peripheral device that stores the on/off state thereof when power is removed from the device Mar 14, 1999 Issued
Array ( [id] => 4349364 [patent_doc_number] => 06321284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Multiprocessor system with multiple memory buses for access to shared memories' [patent_app_type] => 1 [patent_app_number] => 9/268426 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6516 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321284.pdf [firstpage_image] =>[orig_patent_app_number] => 268426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268426
Multiprocessor system with multiple memory buses for access to shared memories Mar 11, 1999 Issued
Array ( [id] => 4366018 [patent_doc_number] => 06286070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Shared memory access device and method' [patent_app_type] => 1 [patent_app_number] => 9/257040 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5118 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286070.pdf [firstpage_image] =>[orig_patent_app_number] => 257040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257040
Shared memory access device and method Feb 24, 1999 Issued
Array ( [id] => 4387843 [patent_doc_number] => 06275880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Framing codes for high-speed parallel data buses' [patent_app_type] => 1 [patent_app_number] => 9/253537 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2725 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275880.pdf [firstpage_image] =>[orig_patent_app_number] => 253537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253537
Framing codes for high-speed parallel data buses Feb 21, 1999 Issued
Array ( [id] => 4133008 [patent_doc_number] => 06047348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'System and method for supporting a multiple width memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/252657 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5557 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047348.pdf [firstpage_image] =>[orig_patent_app_number] => 252657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252657
System and method for supporting a multiple width memory subsystem Feb 18, 1999 Issued
Array ( [id] => 4333487 [patent_doc_number] => 06332196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Disk storage apparatus and power supply control method for the same' [patent_app_type] => 1 [patent_app_number] => 9/244421 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 15466 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332196.pdf [firstpage_image] =>[orig_patent_app_number] => 244421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244421
Disk storage apparatus and power supply control method for the same Feb 3, 1999 Issued
Array ( [id] => 4346134 [patent_doc_number] => 06330631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Data alignment between buses' [patent_app_type] => 1 [patent_app_number] => 9/243169 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 9509 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330631.pdf [firstpage_image] =>[orig_patent_app_number] => 243169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243169
Data alignment between buses Feb 2, 1999 Issued
Array ( [id] => 1481681 [patent_doc_number] => 06345332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Bus interchange apparatus and dual system for accessing a fault information register without regard to buffer conditions' [patent_app_type] => B1 [patent_app_number] => 09/243386 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 8604 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345332.pdf [firstpage_image] =>[orig_patent_app_number] => 09243386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243386
Bus interchange apparatus and dual system for accessing a fault information register without regard to buffer conditions Jan 31, 1999 Issued
Array ( [id] => 4304540 [patent_doc_number] => 06269415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for transferring data over an address bus' [patent_app_type] => 1 [patent_app_number] => 9/230597 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5763 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269415.pdf [firstpage_image] =>[orig_patent_app_number] => 230597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/230597
Method for transferring data over an address bus Jan 25, 1999 Issued
Array ( [id] => 4203935 [patent_doc_number] => 06161187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Skipping clock interrupts during system inactivity to reduce power consumption' [patent_app_type] => 1 [patent_app_number] => 9/232009 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5361 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161187.pdf [firstpage_image] =>[orig_patent_app_number] => 232009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232009
Skipping clock interrupts during system inactivity to reduce power consumption Jan 13, 1999 Issued
Array ( [id] => 4402039 [patent_doc_number] => 06279067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for detecting interrupt requests in video graphics and other systems' [patent_app_type] => 1 [patent_app_number] => 9/231394 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4629 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279067.pdf [firstpage_image] =>[orig_patent_app_number] => 231394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231394
Method and apparatus for detecting interrupt requests in video graphics and other systems Jan 12, 1999 Issued
Array ( [id] => 1540010 [patent_doc_number] => 06338107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method and system for providing hot plug of adapter cards in an expanded slot environment' [patent_app_type] => B1 [patent_app_number] => 09/213056 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6718 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338107.pdf [firstpage_image] =>[orig_patent_app_number] => 09213056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213056
Method and system for providing hot plug of adapter cards in an expanded slot environment Dec 15, 1998 Issued
Array ( [id] => 4373901 [patent_doc_number] => 06292863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'PC card' [patent_app_type] => 1 [patent_app_number] => 9/201904 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8803 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292863.pdf [firstpage_image] =>[orig_patent_app_number] => 201904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201904
PC card Nov 29, 1998 Issued
Array ( [id] => 4177066 [patent_doc_number] => 06105099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method for synchronizing use of dual and solo locking for two competing processors responsive to membership changes' [patent_app_type] => 1 [patent_app_number] => 9/203102 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9572 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105099.pdf [firstpage_image] =>[orig_patent_app_number] => 203102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203102
Method for synchronizing use of dual and solo locking for two competing processors responsive to membership changes Nov 29, 1998 Issued
Array ( [id] => 4424668 [patent_doc_number] => 06266776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'ACPI sleep control' [patent_app_type] => 1 [patent_app_number] => 9/199439 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5553 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266776.pdf [firstpage_image] =>[orig_patent_app_number] => 199439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199439
ACPI sleep control Nov 24, 1998 Issued
Array ( [id] => 4325225 [patent_doc_number] => 06253275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Interrupt gating method for PCI bridges' [patent_app_type] => 1 [patent_app_number] => 9/199967 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2661 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253275.pdf [firstpage_image] =>[orig_patent_app_number] => 199967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199967
Interrupt gating method for PCI bridges Nov 24, 1998 Issued
Array ( [id] => 4400826 [patent_doc_number] => 06304978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method and apparatus for control of the rate of change of current consumption of an electronic component' [patent_app_type] => 1 [patent_app_number] => 9/199891 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3725 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304978.pdf [firstpage_image] =>[orig_patent_app_number] => 199891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199891
Method and apparatus for control of the rate of change of current consumption of an electronic component Nov 23, 1998 Issued
Array ( [id] => 1513213 [patent_doc_number] => 06442640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for determining an address uniquely identifying a hardware component on a common bus' [patent_app_type] => B1 [patent_app_number] => 09/198289 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3196 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442640.pdf [firstpage_image] =>[orig_patent_app_number] => 09198289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198289
Method and apparatus for determining an address uniquely identifying a hardware component on a common bus Nov 22, 1998 Issued
Array ( [id] => 1539108 [patent_doc_number] => 06412037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Interface configuration for connecting different types of busses to a peripheral bus' [patent_app_type] => B1 [patent_app_number] => 09/195485 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2016 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412037.pdf [firstpage_image] =>[orig_patent_app_number] => 09195485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195485
Interface configuration for connecting different types of busses to a peripheral bus Nov 17, 1998 Issued
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