Search

Mitchell Hill

Examiner (ID: 19564)

Most Active Art Unit
3106
Art Unit(s)
3106, 2899
Total Applications
1496
Issued Applications
1329
Pending Applications
6
Abandoned Applications
161

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4101156 [patent_doc_number] => 06018803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period' [patent_app_type] => 1 [patent_app_number] => 8/768913 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5183 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018803.pdf [firstpage_image] =>[orig_patent_app_number] => 768913 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768913
Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period Dec 16, 1996 Issued
Array ( [id] => 3745484 [patent_doc_number] => 05694584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Information processing system capable of quickly processing a parameter and a command necessary for drawing processing' [patent_app_type] => 1 [patent_app_number] => 8/761864 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694584.pdf [firstpage_image] =>[orig_patent_app_number] => 761864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761864
Information processing system capable of quickly processing a parameter and a command necessary for drawing processing Dec 8, 1996 Issued
Array ( [id] => 3997465 [patent_doc_number] => 05961648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Heater preheating device for cathode ray tube' [patent_app_type] => 1 [patent_app_number] => 8/764070 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5598 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961648.pdf [firstpage_image] =>[orig_patent_app_number] => 764070 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764070
Heater preheating device for cathode ray tube Dec 5, 1996 Issued
Array ( [id] => 3974239 [patent_doc_number] => 05901296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus' [patent_app_type] => 1 [patent_app_number] => 8/760914 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3536 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901296.pdf [firstpage_image] =>[orig_patent_app_number] => 760914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760914
Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus Dec 5, 1996 Issued
Array ( [id] => 4023360 [patent_doc_number] => 05889969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure' [patent_app_type] => 1 [patent_app_number] => 8/737951 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6272 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889969.pdf [firstpage_image] =>[orig_patent_app_number] => 737951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/737951
Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure Nov 26, 1996 Issued
Array ( [id] => 4151656 [patent_doc_number] => 06122444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and apparatus for manipulation of digital data in multiple parallel but incongruent buffers' [patent_app_type] => 1 [patent_app_number] => 8/758232 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4571 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122444.pdf [firstpage_image] =>[orig_patent_app_number] => 758232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758232
Method and apparatus for manipulation of digital data in multiple parallel but incongruent buffers Nov 26, 1996 Issued
Array ( [id] => 4040404 [patent_doc_number] => 05884055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource' [patent_app_type] => 1 [patent_app_number] => 8/753673 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 21715 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884055.pdf [firstpage_image] =>[orig_patent_app_number] => 753673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753673
Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource Nov 26, 1996 Issued
Array ( [id] => 3983943 [patent_doc_number] => 05887148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'System for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizes' [patent_app_type] => 1 [patent_app_number] => 8/757252 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5552 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887148.pdf [firstpage_image] =>[orig_patent_app_number] => 757252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757252
System for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizes Nov 26, 1996 Issued
Array ( [id] => 1580263 [patent_doc_number] => 06470409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Interface system having a programmable number of channels and methods of implementing same' [patent_app_type] => B1 [patent_app_number] => 08/757035 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 11443 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470409.pdf [firstpage_image] =>[orig_patent_app_number] => 08757035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757035
Interface system having a programmable number of channels and methods of implementing same Nov 25, 1996 Issued
Array ( [id] => 4081305 [patent_doc_number] => 05867671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Virtual device for performing an operation in response to a SCSI command different than the operation of a SCSI device responding to the SCSI command' [patent_app_type] => 1 [patent_app_number] => 8/752765 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2099 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867671.pdf [firstpage_image] =>[orig_patent_app_number] => 752765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752765
Virtual device for performing an operation in response to a SCSI command different than the operation of a SCSI device responding to the SCSI command Nov 19, 1996 Issued
Array ( [id] => 4070095 [patent_doc_number] => 05864686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method for dynamic address coding for memory mapped commands directed to a system bus and/or secondary bused' [patent_app_type] => 1 [patent_app_number] => 8/751351 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2978 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864686.pdf [firstpage_image] =>[orig_patent_app_number] => 751351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751351
Method for dynamic address coding for memory mapped commands directed to a system bus and/or secondary bused Nov 18, 1996 Issued
Array ( [id] => 4047776 [patent_doc_number] => 05857085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Interface device for XT/AT system devices on high speed local bus' [patent_app_type] => 1 [patent_app_number] => 8/746645 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5611 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857085.pdf [firstpage_image] =>[orig_patent_app_number] => 746645 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746645
Interface device for XT/AT system devices on high speed local bus Nov 12, 1996 Issued
Array ( [id] => 3826202 [patent_doc_number] => 05832242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Inter-chip bus with equal access between masters without arbitration' [patent_app_type] => 1 [patent_app_number] => 8/731851 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15049 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832242.pdf [firstpage_image] =>[orig_patent_app_number] => 731851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731851
Inter-chip bus with equal access between masters without arbitration Oct 20, 1996 Issued
Array ( [id] => 3897301 [patent_doc_number] => 05805845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method for loading memory with program and data information from PC memory across a bridging bus' [patent_app_type] => 1 [patent_app_number] => 8/731852 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805845.pdf [firstpage_image] =>[orig_patent_app_number] => 731852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731852
Method for loading memory with program and data information from PC memory across a bridging bus Oct 20, 1996 Issued
Array ( [id] => 3918662 [patent_doc_number] => 05898848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Inter-chip bus structure for moving multiple isochronous data streams between integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/734754 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15203 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898848.pdf [firstpage_image] =>[orig_patent_app_number] => 734754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/734754
Inter-chip bus structure for moving multiple isochronous data streams between integrated circuits Oct 20, 1996 Issued
Array ( [id] => 4224340 [patent_doc_number] => 06079022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity' [patent_app_type] => 1 [patent_app_number] => 8/728716 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4209 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079022.pdf [firstpage_image] =>[orig_patent_app_number] => 728716 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728716
Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity Oct 10, 1996 Issued
Array ( [id] => 4081335 [patent_doc_number] => 05867673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Universal operator station module for a distributed process control system' [patent_app_type] => 1 [patent_app_number] => 8/727724 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5173 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867673.pdf [firstpage_image] =>[orig_patent_app_number] => 727724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727724
Universal operator station module for a distributed process control system Oct 6, 1996 Issued
Array ( [id] => 3936003 [patent_doc_number] => 05915119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Proxy terminal for network controlling of power managed user terminals in suspend mode' [patent_app_type] => 1 [patent_app_number] => 8/724653 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3812 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915119.pdf [firstpage_image] =>[orig_patent_app_number] => 724653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724653
Proxy terminal for network controlling of power managed user terminals in suspend mode Sep 30, 1996 Issued
Array ( [id] => 3779344 [patent_doc_number] => 05845138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'CPU power management in non-APM systems' [patent_app_type] => 1 [patent_app_number] => 8/723745 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2500 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845138.pdf [firstpage_image] =>[orig_patent_app_number] => 723745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723745
CPU power management in non-APM systems Sep 29, 1996 Issued
Array ( [id] => 4026033 [patent_doc_number] => 05941970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Address/data queuing arrangement and method for providing high data through-put across bus bridge' [patent_app_type] => 1 [patent_app_number] => 8/721252 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7706 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941970.pdf [firstpage_image] =>[orig_patent_app_number] => 721252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721252
Address/data queuing arrangement and method for providing high data through-put across bus bridge Sep 25, 1996 Issued
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