Mitchell Hill

Array ( [id] => 1580256 [patent_doc_number] => 06470407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method for arbitrating interrupt priorities among peripherals in a microprocessor-based system' [patent_app_type] => B1 [patent_app_number] => 09/490961 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3128 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470407.pdf [firstpage_image] =>[orig_patent_app_number] => 09490961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418522 [patent_doc_number] => 06546445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and system for connecting dual storage interfaces' [patent_app_type] => B1 [patent_app_number] => 09/482231 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546445.pdf [firstpage_image] =>[orig_patent_app_number] => 09482231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644149 [patent_doc_number] => 06473825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Apparatus and method for controlling secure communications between peripheral components on computer buses connected by a bridge circuit' [patent_app_type] => B1 [patent_app_number] => 09/481331 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4923 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473825.pdf [firstpage_image] =>[orig_patent_app_number] => 09481331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431356 [patent_doc_number] => 06519663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Simple enclosure services (SES) using a high-speed, point-to-point, serial bus' [patent_app_type] => B1 [patent_app_number] => 09/481537 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4637 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519663.pdf [firstpage_image] =>[orig_patent_app_number] => 09481537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423353 [patent_doc_number] => 06539445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method for load balancing in an application server system' [patent_app_type] => B1 [patent_app_number] => 09/481101 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 15 [patent_no_of_words] => 7958 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539445.pdf [firstpage_image] =>[orig_patent_app_number] => 09481101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521648 [patent_doc_number] => 06502148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'System for scaling an application server system' [patent_app_type] => B1 [patent_app_number] => 09/480318 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7987 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502148.pdf [firstpage_image] =>[orig_patent_app_number] => 09480318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1376697 [patent_doc_number] => 06578099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method and computer system for safely hot-plugging adapter cards' [patent_app_type] => B1 [patent_app_number] => 09/477756 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4685 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578099.pdf [firstpage_image] =>[orig_patent_app_number] => 09477756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1376651 [patent_doc_number] => 06578096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method and system for efficient I/O operation completion in a fibre channel node' [patent_app_type] => B1 [patent_app_number] => 09/475907 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9687 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578096.pdf [firstpage_image] =>[orig_patent_app_number] => 09475907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1485123 [patent_doc_number] => 06453422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Reference voltage distribution for multiload i/o systems' [patent_app_type] => B1 [patent_app_number] => 09/470686 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6162 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453422.pdf [firstpage_image] =>[orig_patent_app_number] => 09470686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426893 [patent_doc_number] => 06195724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Methods and apparatus for prioritization of access to external devices' [patent_app_type] => 1 [patent_app_number] => 9/439860 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 15539 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195724.pdf [firstpage_image] =>[orig_patent_app_number] => 439860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567224 [patent_doc_number] => 06438632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Electronic bulletin board system' [patent_app_type] => B1 [patent_app_number] => 09/423599 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438632.pdf [firstpage_image] =>[orig_patent_app_number] => 09423599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444059 [patent_doc_number] => 06496896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Transmission apparatus, recording apparatus, transmission and reception apparatus, transmission method, recording method and transmission and reception method' [patent_app_type] => B1 [patent_app_number] => 09/435639 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 114 [patent_no_of_words] => 42543 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496896.pdf [firstpage_image] =>[orig_patent_app_number] => 09435639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361010 [patent_doc_number] => 06587904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method and apparatus for preventing loops in a full-duplex bus' [patent_app_type] => B1 [patent_app_number] => 09/435160 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 5909 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587904.pdf [firstpage_image] =>[orig_patent_app_number] => 09435160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630025 [patent_doc_number] => 06636914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases' [patent_app_type] => B1 [patent_app_number] => 09/435134 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5424 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636914.pdf [firstpage_image] =>[orig_patent_app_number] => 09435134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280438 [patent_doc_number] => 06260091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply' [patent_app_type] => 1 [patent_app_number] => 9/434080 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11198 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260091.pdf [firstpage_image] =>[orig_patent_app_number] => 434080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1376682 [patent_doc_number] => 06578098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Predictive mechanism for ASB slave responses' [patent_app_type] => B1 [patent_app_number] => 09/435133 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6296 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578098.pdf [firstpage_image] =>[orig_patent_app_number] => 09435133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549524 [patent_doc_number] => 06374321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Mechanisms for converting address and data signals to interrupt message signals' [patent_app_type] => B1 [patent_app_number] => 09/428682 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5940 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374321.pdf [firstpage_image] =>[orig_patent_app_number] => 09428682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431863 [patent_doc_number] => 06516378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Microprocessor for controlling busses' [patent_app_type] => B1 [patent_app_number] => 09/426757 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 10841 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516378.pdf [firstpage_image] =>[orig_patent_app_number] => 09426757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4334922 [patent_doc_number] => 06243777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Circuit for preventing bus contention' [patent_app_type] => 1 [patent_app_number] => 9/426634 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4246 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243777.pdf [firstpage_image] =>[orig_patent_app_number] => 426634 [rel_patent_id] =>[rel_patent_doc_number] =>)