Mitchell Hill

Array ( [id] => 1587300 [patent_doc_number] => 06425029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Apparatus for configuring bus architecture through software control' [patent_app_type] => B1 [patent_app_number] => 09/327413 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425029.pdf [firstpage_image] =>[orig_patent_app_number] => 09327413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557456 [patent_doc_number] => 06401151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for configuring bus architecture through software control' [patent_app_type] => B1 [patent_app_number] => 09/327412 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2536 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401151.pdf [firstpage_image] =>[orig_patent_app_number] => 09327412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587288 [patent_doc_number] => 06425025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'System and method for connecting electronic circuitry in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/325688 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425025.pdf [firstpage_image] =>[orig_patent_app_number] => 09325688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1438651 [patent_doc_number] => 06356970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Interrupt request control module with a DSP interrupt vector generator' [patent_app_type] => B1 [patent_app_number] => 09/322955 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356970.pdf [firstpage_image] =>[orig_patent_app_number] => 09322955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1519722 [patent_doc_number] => 06421783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Microprocessor and main board mounting arrangement' [patent_app_type] => B1 [patent_app_number] => 09/321109 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 675 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421783.pdf [firstpage_image] =>[orig_patent_app_number] => 09321109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521664 [patent_doc_number] => 06502151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Data-processing arrangement including an interrupt generator' [patent_app_type] => B2 [patent_app_number] => 09/320809 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5421 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502151.pdf [firstpage_image] =>[orig_patent_app_number] => 09320809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1526543 [patent_doc_number] => 06353893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Sleep mode indicator for a battery-operated device' [patent_app_type] => B1 [patent_app_number] => 09/317742 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353893.pdf [firstpage_image] =>[orig_patent_app_number] => 09317742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568627 [patent_doc_number] => 06339807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Multiprocessor system and the bus arbitrating method of the same' [patent_app_type] => B1 [patent_app_number] => 09/310942 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5494 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339807.pdf [firstpage_image] =>[orig_patent_app_number] => 09310942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466735 [patent_doc_number] => 06351820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'PC card with automated drag and sleep function' [patent_app_type] => B1 [patent_app_number] => 09/298614 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351820.pdf [firstpage_image] =>[orig_patent_app_number] => 09298614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4292033 [patent_doc_number] => 06247085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for removable peripheral user interface panels' [patent_app_type] => 1 [patent_app_number] => 9/285875 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247085.pdf [firstpage_image] =>[orig_patent_app_number] => 285875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1505948 [patent_doc_number] => 06487628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Peripheral component interface with multiple data channels and reduced latency over a system area network' [patent_app_type] => B1 [patent_app_number] => 09/283773 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8167 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487628.pdf [firstpage_image] =>[orig_patent_app_number] => 09283773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495269 [patent_doc_number] => 06418501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Memory card' [patent_app_type] => B1 [patent_app_number] => 09/280708 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418501.pdf [firstpage_image] =>[orig_patent_app_number] => 09280708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1572284 [patent_doc_number] => 06378027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'System upgrade and processor service' [patent_app_type] => B1 [patent_app_number] => 09/281080 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378027.pdf [firstpage_image] =>[orig_patent_app_number] => 09281080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324437 [patent_doc_number] => 06327635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Add-on card with automatic bus power line selection circuit' [patent_app_type] => 1 [patent_app_number] => 9/281369 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3393 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327635.pdf [firstpage_image] =>[orig_patent_app_number] => 281369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459971 [patent_doc_number] => 06463495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Command and control infrastructure for a computer system using the computer\'s power rail' [patent_app_type] => B1 [patent_app_number] => 09/280311 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463495.pdf [firstpage_image] =>[orig_patent_app_number] => 09280311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604468 [patent_doc_number] => 06434654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System bus with a variable width selectivity configurable at initialization' [patent_app_type] => B1 [patent_app_number] => 09/277569 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434654.pdf [firstpage_image] =>[orig_patent_app_number] => 09277569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4387893 [patent_doc_number] => 06275884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for interconnecting components within a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/276383 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275884.pdf [firstpage_image] =>[orig_patent_app_number] => 276383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568622 [patent_doc_number] => 06339806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Primary bus to secondary bus multiplexing for I2C and other serial buses' [patent_app_type] => B1 [patent_app_number] => 09/273663 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2759 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339806.pdf [firstpage_image] =>[orig_patent_app_number] => 09273663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1526411 [patent_doc_number] => 06353865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Terminator with indicator' [patent_app_type] => B1 [patent_app_number] => 09/273454 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2664 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353865.pdf [firstpage_image] =>[orig_patent_app_number] => 09273454 [rel_patent_id] =>[rel_patent_doc_number] =>)