Mohammad M Ali
Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )
Most Active Art Unit | 3744 |
Art Unit(s) | 3784, 3744 |
Total Applications | 2900 |
Issued Applications | 2328 |
Pending Applications | 41 |
Abandoned Applications | 531 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17536691
[patent_doc_number] => 20220115300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/187961
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7859
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187961
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187961 | Semiconductor device resistant to thermal cracking and manufacturing method thereof | Feb 28, 2021 | Issued |
Array
(
[id] => 16936585
[patent_doc_number] => 20210202474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES FORMED ON HIGHLY DOPED SEMICONDUCTOR
[patent_app_type] => utility
[patent_app_number] => 17/181613
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181613
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/181613 | Heterolithic integrated circuits including integrated devices formed on semiconductor materials of different elemental composition | Feb 21, 2021 | Issued |
Array
(
[id] => 19524158
[patent_doc_number] => 12125899
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => MOS transistor having substantially parallelepiped-shaped insulating spacers
[patent_app_type] => utility
[patent_app_number] => 17/180197
[patent_app_country] => US
[patent_app_date] => 2021-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 2990
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180197
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/180197 | MOS transistor having substantially parallelepiped-shaped insulating spacers | Feb 18, 2021 | Issued |
Array
(
[id] => 16888993
[patent_doc_number] => 20210175190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => Pattern Polymer Layer to Reduce Stress
[patent_app_type] => utility
[patent_app_number] => 17/178491
[patent_app_country] => US
[patent_app_date] => 2021-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7433
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178491
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/178491 | Method for manufacturing a semiconductor device including patterning a polymer layer to reduce stress | Feb 17, 2021 | Issued |
Array
(
[id] => 17781011
[patent_doc_number] => 20220247361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => Power Amplifier Linearizer
[patent_app_type] => utility
[patent_app_number] => 17/165493
[patent_app_country] => US
[patent_app_date] => 2021-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5741
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165493
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/165493 | Power amplifier linearizer | Feb 1, 2021 | Issued |
Array
(
[id] => 17781008
[patent_doc_number] => 20220247358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => Power Amplifier Equalizer
[patent_app_type] => utility
[patent_app_number] => 17/165198
[patent_app_country] => US
[patent_app_date] => 2021-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11754
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165198
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/165198 | Power amplifier equalizer | Feb 1, 2021 | Issued |
Array
(
[id] => 17010996
[patent_doc_number] => 20210242157
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL
[patent_app_type] => utility
[patent_app_number] => 17/162595
[patent_app_country] => US
[patent_app_date] => 2021-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162595
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/162595 | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal | Jan 28, 2021 | Issued |
Array
(
[id] => 19428264
[patent_doc_number] => 12087698
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Wiring substrate, array substrate and light emitting module having control regions arranged into control region rows and control region columns
[patent_app_type] => utility
[patent_app_number] => 17/426815
[patent_app_country] => US
[patent_app_date] => 2021-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 50
[patent_no_of_words] => 44226
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 909
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426815
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/426815 | Wiring substrate, array substrate and light emitting module having control regions arranged into control region rows and control region columns | Jan 27, 2021 | Issued |
Array
(
[id] => 17026133
[patent_doc_number] => 20210250005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => DIFFERENTIAL AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 17/160755
[patent_app_country] => US
[patent_app_date] => 2021-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160755
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/160755 | Differential amplifier | Jan 27, 2021 | Issued |
Array
(
[id] => 17011684
[patent_doc_number] => 20210242845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => DIFFERENTIAL AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 17/159163
[patent_app_country] => US
[patent_app_date] => 2021-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8104
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159163
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/159163 | Differential amplifier | Jan 26, 2021 | Issued |
Array
(
[id] => 18481213
[patent_doc_number] => 11694968
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-04
[patent_title] => Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
[patent_app_type] => utility
[patent_app_number] => 17/157374
[patent_app_country] => US
[patent_app_date] => 2021-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 24
[patent_no_of_words] => 6150
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157374
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/157374 | Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate | Jan 24, 2021 | Issued |
Array
(
[id] => 18481615
[patent_doc_number] => 11695374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-04
[patent_title] => Fast settling ripple reduction loop for high speed precision chopper amplifiers
[patent_app_type] => utility
[patent_app_number] => 17/152872
[patent_app_country] => US
[patent_app_date] => 2021-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5109
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152872
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/152872 | Fast settling ripple reduction loop for high speed precision chopper amplifiers | Jan 19, 2021 | Issued |
Array
(
[id] => 17738072
[patent_doc_number] => 20220223534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => PACKAGE STRUCTURE INCLUDING A FIRST DIE AND A SECOND DIE AND A BRIDGE DIE AND METHOD OF FORMING THE PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/148568
[patent_app_country] => US
[patent_app_date] => 2021-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148568
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148568 | Package structure including a first die and a second die and a bridge die and method of forming the package structure | Jan 13, 2021 | Issued |
Array
(
[id] => 17723431
[patent_doc_number] => 20220216153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-07
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/144061
[patent_app_country] => US
[patent_app_date] => 2021-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12631
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144061
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144061 | Semiconductor package having molded die and semiconductor die and manufacturing method thereof | Jan 6, 2021 | Issued |
Array
(
[id] => 18919530
[patent_doc_number] => 11881826
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-23
[patent_title] => Audio amplifier circuitry
[patent_app_type] => utility
[patent_app_number] => 17/142904
[patent_app_country] => US
[patent_app_date] => 2021-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 10807
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142904
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/142904 | Audio amplifier circuitry | Jan 5, 2021 | Issued |
Array
(
[id] => 18277521
[patent_doc_number] => 11616475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Amplifier gain-tuning circuits and methods
[patent_app_type] => utility
[patent_app_number] => 17/141726
[patent_app_country] => US
[patent_app_date] => 2021-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6700
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141726
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/141726 | Amplifier gain-tuning circuits and methods | Jan 4, 2021 | Issued |
Array
(
[id] => 17475524
[patent_doc_number] => 20220083028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => SIGNAL GAIN DETERMINATION CIRCUIT AND SIGNAL GAIN DETERMINATION METHOD
[patent_app_type] => utility
[patent_app_number] => 17/141161
[patent_app_country] => US
[patent_app_date] => 2021-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/141161 | Signal gain determination circuit and signal gain determination method | Jan 3, 2021 | Issued |
Array
(
[id] => 19154191
[patent_doc_number] => 11979116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-07
[patent_title] => Enhanced amplifier topology in an analog front end (AFE)
[patent_app_type] => utility
[patent_app_number] => 17/137685
[patent_app_country] => US
[patent_app_date] => 2020-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8161
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137685
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/137685 | Enhanced amplifier topology in an analog front end (AFE) | Dec 29, 2020 | Issued |
Array
(
[id] => 17233091
[patent_doc_number] => 20210359648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => IMPEDANCE ADJUSTMENT CIRCUIT AND METHOD, BIAS CIRCUIT STRUCTURE AND AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 17/138783
[patent_app_country] => US
[patent_app_date] => 2020-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138783
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/138783 | Impedance adjustment circuit and method, bias circuit structure and amplifier | Dec 29, 2020 | Issued |
Array
(
[id] => 17509358
[patent_doc_number] => 20220102461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => DISPLAY DEVICE, DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL
[patent_app_type] => utility
[patent_app_number] => 17/427074
[patent_app_country] => US
[patent_app_date] => 2020-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8035
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427074
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/427074 | DISPLAY DEVICE, DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL | Dec 28, 2020 | Pending |