Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17971942 [patent_doc_number] => 11489497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Bias circuit [patent_app_type] => utility [patent_app_number] => 16/925533 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925533
Bias circuit Jul 9, 2020 Issued
Array ( [id] => 16579446 [patent_doc_number] => 20210013847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => POWER AMPLIFIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/923493 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923493
POWER AMPLIFIER CIRCUIT Jul 7, 2020 Pending
Array ( [id] => 18137258 [patent_doc_number] => 11562947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Semiconductor package having a conductive pad with an anchor flange [patent_app_type] => utility [patent_app_number] => 16/920908 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 2588 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920908 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920908
Semiconductor package having a conductive pad with an anchor flange Jul 5, 2020 Issued
Array ( [id] => 17159068 [patent_doc_number] => 20210320119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/920201 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920201
Three-dimensional memory device including a peripheral circuit and a memory stack Jul 1, 2020 Issued
Array ( [id] => 17971290 [patent_doc_number] => 11488838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor device having an embedded conductive layer for power/ground planes in Fo-eWLB [patent_app_type] => utility [patent_app_number] => 16/918643 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 12542 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918643
Semiconductor device having an embedded conductive layer for power/ground planes in Fo-eWLB Jun 30, 2020 Issued
Array ( [id] => 16395171 [patent_doc_number] => 20200336112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => VALLEY DETECTION FOR SUPPLY VOLTAGE MODULATION IN POWER AMPLIFIER CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/916155 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916155
Valley detection for supply voltage modulation in power amplifier circuits Jun 29, 2020 Issued
Array ( [id] => 18494256 [patent_doc_number] => 11699677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Die-to-wafer bonding utilizing micro-transfer printing [patent_app_type] => utility [patent_app_number] => 16/917492 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5108 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917492
Die-to-wafer bonding utilizing micro-transfer printing Jun 29, 2020 Issued
Array ( [id] => 17217704 [patent_doc_number] => 20210351042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/913020 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913020 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913020
Semiconductor package having semiconductor element with pins and formation method thereof Jun 25, 2020 Issued
Array ( [id] => 16545004 [patent_doc_number] => 20200411419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => ELECTRONIC COMPONENT APPARATUS [patent_app_type] => utility [patent_app_number] => 16/912969 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912969
Electronic component apparatus having a first lead frame and a second lead frame and an electronic component provided between the first lead frame and the second lead frame Jun 25, 2020 Issued
Array ( [id] => 18156796 [patent_doc_number] => 11569797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Transconductor circuits with programmable tradeoff between bandwidth and flicker noise [patent_app_type] => utility [patent_app_number] => 16/910994 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910994
Transconductor circuits with programmable tradeoff between bandwidth and flicker noise Jun 23, 2020 Issued
Array ( [id] => 16364699 [patent_doc_number] => 20200321450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => METHOD OF FORMING EPITAXIAL FIN STRUCTURES OF FINFET [patent_app_type] => utility [patent_app_number] => 16/908057 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908057
Epitaxial fin structures having an epitaxial buffer region and an epitaxial capping region Jun 21, 2020 Issued
Array ( [id] => 19378324 [patent_doc_number] => 12069924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Display substrate and manufacturing method thereof, and display device having a plurality of apertures in a one-to-one correspondence to a plurality of first electrodes [patent_app_type] => utility [patent_app_number] => 17/416078 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 25995 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 863 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17416078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/416078
Display substrate and manufacturing method thereof, and display device having a plurality of apertures in a one-to-one correspondence to a plurality of first electrodes Jun 18, 2020 Issued
Array ( [id] => 19094464 [patent_doc_number] => 11955935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Signal processing device and adjusting method [patent_app_type] => utility [patent_app_number] => 17/423068 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10564 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17423068 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/423068
Signal processing device and adjusting method Jun 15, 2020 Issued
Array ( [id] => 17247178 [patent_doc_number] => 20210366923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => MEMORY DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/901786 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901786
Memory device having staircase structure including word line tiers and formation method thereof Jun 14, 2020 Issued
Array ( [id] => 17353298 [patent_doc_number] => 11227945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Transistor having at least one transistor cell with a field electrode [patent_app_type] => utility [patent_app_number] => 16/895755 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 8506 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895755
Transistor having at least one transistor cell with a field electrode Jun 7, 2020 Issued
Array ( [id] => 18190831 [patent_doc_number] => 11581435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor device including a first fin active region, a second fin active region and a field region [patent_app_type] => utility [patent_app_number] => 16/895059 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 14451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895059
Semiconductor device including a first fin active region, a second fin active region and a field region Jun 7, 2020 Issued
Array ( [id] => 16545060 [patent_doc_number] => 20200411475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH [patent_app_type] => utility [patent_app_number] => 16/890053 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890053
Semiconductor package with high routing density patch Jun 1, 2020 Issued
Array ( [id] => 18048550 [patent_doc_number] => 11522510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => High output current transconductance amplifier [patent_app_type] => utility [patent_app_number] => 16/889973 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3601 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889973
High output current transconductance amplifier Jun 1, 2020 Issued
Array ( [id] => 16888970 [patent_doc_number] => 20210175167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/887867 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887867
Semiconductor memory device having capacitor spaced apart from a gate stack structure May 28, 2020 Issued
Array ( [id] => 18032637 [patent_doc_number] => 11515841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => DC coupled amplifier having pre-driver and bias control [patent_app_type] => utility [patent_app_number] => 16/888294 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888294
DC coupled amplifier having pre-driver and bias control May 28, 2020 Issued
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