Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17263823 [patent_doc_number] => 20210376808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => CIRCUITS, EQUALIZERS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/886653 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886653
Circuits, equalizers and related methods May 27, 2020 Issued
Array ( [id] => 18016326 [patent_doc_number] => 11508633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Package structure having taper-shaped conductive pillar and method of forming thereof [patent_app_type] => utility [patent_app_number] => 16/886755 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 103 [patent_no_of_words] => 20989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886755
Package structure having taper-shaped conductive pillar and method of forming thereof May 27, 2020 Issued
Array ( [id] => 16928384 [patent_doc_number] => 11049876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Three-dimensional memory device containing through-memory-level contact via structures [patent_app_type] => utility [patent_app_number] => 16/881353 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 140 [patent_no_of_words] => 34559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881353
Three-dimensional memory device containing through-memory-level contact via structures May 21, 2020 Issued
Array ( [id] => 17332445 [patent_doc_number] => 11222913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Image sensor device having first lens over a light-sensing region and surrounded by a grid layer [patent_app_type] => utility [patent_app_number] => 16/881854 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881854
Image sensor device having first lens over a light-sensing region and surrounded by a grid layer May 21, 2020 Issued
Array ( [id] => 19093983 [patent_doc_number] => 11955448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches [patent_app_type] => utility [patent_app_number] => 16/880483 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 7545 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880483
Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches May 20, 2020 Issued
Array ( [id] => 18317996 [patent_doc_number] => 11632089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Notch circuit and power amplifier module [patent_app_type] => utility [patent_app_number] => 16/878669 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3055 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878669
Notch circuit and power amplifier module May 19, 2020 Issued
Array ( [id] => 17247116 [patent_doc_number] => 20210366861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => Hybrid Thermal Interface Material and Low Temperature Solder Patterns to Improve Package Warpage and Reliability [patent_app_type] => utility [patent_app_number] => 16/879596 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879596
Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability May 19, 2020 Issued
Array ( [id] => 17410203 [patent_doc_number] => 11251100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/877508 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877508
Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure May 18, 2020 Issued
Array ( [id] => 17764859 [patent_doc_number] => 20220238472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => FLEXIBLE ELECTRONIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/611611 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/611611
FLEXIBLE ELECTRONIC STRUCTURE May 18, 2020 Pending
Array ( [id] => 16928897 [patent_doc_number] => 11050397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Interpolation operational amplifier circuit and display panel [patent_app_type] => utility [patent_app_number] => 16/875342 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10906 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875342
Interpolation operational amplifier circuit and display panel May 14, 2020 Issued
Array ( [id] => 16575298 [patent_doc_number] => 10897229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Compensation circuit for operational amplifier, integrated circuit and display panel [patent_app_type] => utility [patent_app_number] => 16/875220 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12785 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875220
Compensation circuit for operational amplifier, integrated circuit and display panel May 14, 2020 Issued
Array ( [id] => 17501347 [patent_doc_number] => 11290063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Low noise amplifier [patent_app_type] => utility [patent_app_number] => 15/931595 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3714 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931595
Low noise amplifier May 13, 2020 Issued
Array ( [id] => 16731264 [patent_doc_number] => 20210098412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => DIRECT GANG BONDING METHODS AND STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/874527 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874527
Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive May 13, 2020 Issued
Array ( [id] => 16272362 [patent_doc_number] => 20200273850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING A FIRST CELL ROW AND A SECOND CELL ROW [patent_app_type] => utility [patent_app_number] => 15/931171 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931171
Semiconductor device having a first cell row and a second cell row May 12, 2020 Issued
Array ( [id] => 16403004 [patent_doc_number] => 20200343862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => Drain Switched Split Amplifier with Capacitor Switching for Noise Figure and Isolation Improvement in Split Mode [patent_app_type] => utility [patent_app_number] => 15/931236 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931236
Drain switched split amplifier with capacitor switching for noise figure and isolation improvement in split mode May 12, 2020 Issued
Array ( [id] => 16272256 [patent_doc_number] => 20200273744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/930905 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930905
Semiconductor devices May 12, 2020 Issued
Array ( [id] => 17217775 [patent_doc_number] => 20210351113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => Integrated Circuit Having Die Attach Materials with Channels and Process of Implementing the Same [patent_app_type] => utility [patent_app_number] => 16/868639 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868639
Integrated circuit having die attach materials with channels and process of implementing the same May 6, 2020 Issued
Array ( [id] => 17574184 [patent_doc_number] => 11322458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Semiconductor structure including a first substrate and a second substrate and a buffer structure in the second substrate [patent_app_type] => utility [patent_app_number] => 16/860041 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3866 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860041
Semiconductor structure including a first substrate and a second substrate and a buffer structure in the second substrate Apr 26, 2020 Issued
Array ( [id] => 16660734 [patent_doc_number] => 20210057371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/854114 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854114
Semiconductor devices including bonding layer and adsorption layer Apr 20, 2020 Issued
Array ( [id] => 16211241 [patent_doc_number] => 20200244231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => CARTESIAN FEEDBACK CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/851284 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851284
Cartesian feedback circuit Apr 16, 2020 Issued
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