Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18410609 [patent_doc_number] => 20230171962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material [patent_app_type] => utility [patent_app_number] => 18/096341 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096341
Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material Jan 11, 2023 Issued
Array ( [id] => 18349689 [patent_doc_number] => 20230137800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/090918 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090918
Semiconductor package having a semiconductor element and a wiring structure Dec 28, 2022 Issued
Array ( [id] => 19063639 [patent_doc_number] => 11942902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Methods related to power amplification systems with adjustable common base bias [patent_app_type] => utility [patent_app_number] => 18/090441 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090441
Methods related to power amplification systems with adjustable common base bias Dec 27, 2022 Issued
Array ( [id] => 18679970 [patent_doc_number] => 20230317628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => PROTECTIVE ELEMENTS FOR BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/087705 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/087705
PROTECTIVE ELEMENTS FOR BONDED STRUCTURES Dec 21, 2022 Pending
Array ( [id] => 18320028 [patent_doc_number] => 20230118156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => LAYER STRUCTURES FOR MAKING DIRECT METAL-TO-METAL BONDS AT LOW TEMPERATURES IN MICROELECTRONICS [patent_app_type] => utility [patent_app_number] => 18/069485 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069485 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069485
LAYER STRUCTURES FOR MAKING DIRECT METAL-TO-METAL BONDS AT LOW TEMPERATURES IN MICROELECTRONICS Dec 20, 2022 Pending
Array ( [id] => 18320614 [patent_doc_number] => 20230118742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 18/083339 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083339
Semiconductor devices having a conductive layer stacking with an insulating layer and a spacer structure through the conductive layer Dec 15, 2022 Issued
Array ( [id] => 18299587 [patent_doc_number] => 20230109273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => METHOD TO FABRICATE UNIFORM TUNNELING DIELECTRIC OF EMBEDDED FLASH MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/079039 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079039 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079039
Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate Dec 11, 2022 Issued
Array ( [id] => 19610927 [patent_doc_number] => 12159808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Wire bond damage detector including a detection bond pad over a first and a second connected structures [patent_app_type] => utility [patent_app_number] => 18/075288 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4089 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075288
Wire bond damage detector including a detection bond pad over a first and a second connected structures Dec 4, 2022 Issued
Array ( [id] => 18306304 [patent_doc_number] => 20230110204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => PROGRAMMABLE GAIN AMPLIFIER AND A DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER CONTAINING THE PGA [patent_app_type] => utility [patent_app_number] => 18/061512 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061512
PROGRAMMABLE GAIN AMPLIFIER AND A DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER CONTAINING THE PGA Dec 4, 2022 Pending
Array ( [id] => 18858001 [patent_doc_number] => 11855599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Circuits, equalizers and related methods [patent_app_type] => utility [patent_app_number] => 18/060970 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060970
Circuits, equalizers and related methods Dec 1, 2022 Issued
Array ( [id] => 18271078 [patent_doc_number] => 20230092320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION AND A CONTROL LOGIC REGION [patent_app_type] => utility [patent_app_number] => 18/059165 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059165
Microelectronic devices having a memory array region, a control logic region, and signal routing structures Nov 27, 2022 Issued
Array ( [id] => 18271680 [patent_doc_number] => 20230092922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => DC COUPLED AMPLIFIER HAVING PRE-DRIVER AND BIAS CONTROL [patent_app_type] => utility [patent_app_number] => 18/070336 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070336
DC coupled amplifier having pre-driver and bias control Nov 27, 2022 Issued
Array ( [id] => 19000940 [patent_doc_number] => 11917818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Memory device having vertical structure including a first wafer and a second wafer stacked on the first wafer [patent_app_type] => utility [patent_app_number] => 18/058795 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16700 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058795
Memory device having vertical structure including a first wafer and a second wafer stacked on the first wafer Nov 24, 2022 Issued
Array ( [id] => 19183783 [patent_doc_number] => 11990383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Package structure having at least one die with a plurality of taper-shaped die connectors [patent_app_type] => utility [patent_app_number] => 17/979713 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 103 [patent_no_of_words] => 21047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979713
Package structure having at least one die with a plurality of taper-shaped die connectors Nov 1, 2022 Issued
Array ( [id] => 18169672 [patent_doc_number] => 20230036283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/960767 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960767
Package structure with bridge die laterally wrapped by insulating encapsulant and surrounded by through vias and method of forming the package structure Oct 4, 2022 Issued
Array ( [id] => 18875312 [patent_doc_number] => 11863138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Transconductance circuits with degeneration transistors [patent_app_type] => utility [patent_app_number] => 17/959481 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959481
Transconductance circuits with degeneration transistors Oct 3, 2022 Issued
Array ( [id] => 18147761 [patent_doc_number] => 20230021618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/953941 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953941
Organic light-emitting diode display substrate, display panel and display device having an anode layer comprises a common power line provided with vent holes Sep 26, 2022 Issued
Array ( [id] => 18144520 [patent_doc_number] => 20230018372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => METHOD FOR ESTABLISHING A BUILDING AUTOMATION SYSTEM INCLUDING INSTALLING A PLURALITY OF CONTROLLABLE DEVICES IN A PLURALITY OF ROOMS IN A BUILDING [patent_app_type] => utility [patent_app_number] => 17/946605 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946605
METHOD FOR ESTABLISHING A BUILDING AUTOMATION SYSTEM INCLUDING INSTALLING A PLURALITY OF CONTROLLABLE DEVICES IN A PLURALITY OF ROOMS IN A BUILDING Sep 15, 2022 Pending
Array ( [id] => 19539889 [patent_doc_number] => 12132449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Amplification circuit [patent_app_type] => utility [patent_app_number] => 17/932395 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 16982 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932395
Amplification circuit Sep 14, 2022 Issued
Array ( [id] => 19030347 [patent_doc_number] => 11929718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Systems and methods for optimizing amplifier operations [patent_app_type] => utility [patent_app_number] => 17/940612 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940612
Systems and methods for optimizing amplifier operations Sep 7, 2022 Issued
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