Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17070650 [patent_doc_number] => 20210272867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/257938 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17257938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/257938
Silicon carbide semiconductor device including a resin covering a silicon carbide semiconductor chip May 28, 2019 Issued
Array ( [id] => 14843171 [patent_doc_number] => 20190279986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Memory Cells [patent_app_type] => utility [patent_app_number] => 16/421286 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421286
Memory cells having a controlled conductivity region May 22, 2019 Issued
Array ( [id] => 16835237 [patent_doc_number] => 11011497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/417918 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9775 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417918 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417918
Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof May 20, 2019 Issued
Array ( [id] => 17077981 [patent_doc_number] => 11114396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Reduced-length bond pads for broadband power amplifiers [patent_app_type] => utility [patent_app_number] => 16/418361 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4199 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418361
Reduced-length bond pads for broadband power amplifiers May 20, 2019 Issued
Array ( [id] => 16472350 [patent_doc_number] => 20200373888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => POWER AMPLIFIER SYSTEM [patent_app_type] => utility [patent_app_number] => 16/416816 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416816 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416816
Power amplifier system May 19, 2019 Issued
Array ( [id] => 15261197 [patent_doc_number] => 20190379332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => SCHOTTKY ENHANCED BIAS CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/415135 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415135
SCHOTTKY ENHANCED BIAS CIRCUIT May 16, 2019 Abandoned
Array ( [id] => 15824417 [patent_doc_number] => 10637412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Apparatus and methods for low noise amplifiers [patent_app_type] => utility [patent_app_number] => 16/415160 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415160
Apparatus and methods for low noise amplifiers May 16, 2019 Issued
Array ( [id] => 17107619 [patent_doc_number] => 11127847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Semiconductor devices having a gate field plate including an extension portion and methods for fabricating the semiconductor device [patent_app_type] => utility [patent_app_number] => 16/413893 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5861 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413893
Semiconductor devices having a gate field plate including an extension portion and methods for fabricating the semiconductor device May 15, 2019 Issued
Array ( [id] => 16448397 [patent_doc_number] => 10840328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor devices having charge-absorbing structure disposed over substrate and methods for forming the semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/413871 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5787 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413871
Semiconductor devices having charge-absorbing structure disposed over substrate and methods for forming the semiconductor devices May 15, 2019 Issued
Array ( [id] => 17638223 [patent_doc_number] => 11348958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Image sensing device with grid structure and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/414498 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414498
Image sensing device with grid structure and fabrication method thereof May 15, 2019 Issued
Array ( [id] => 16803461 [patent_doc_number] => 10998418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Power semiconductor devices having reflowed inter-metal dielectric layers [patent_app_type] => utility [patent_app_number] => 16/413921 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 13099 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413921
Power semiconductor devices having reflowed inter-metal dielectric layers May 15, 2019 Issued
Array ( [id] => 17309331 [patent_doc_number] => 11210447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices [patent_app_type] => utility [patent_app_number] => 16/414488 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414488 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414488
Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices May 15, 2019 Issued
Array ( [id] => 16456025 [patent_doc_number] => 20200365451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => METHODS OF FORMING INTERCONNECT STRUCTURES USING VIA HOLES FILLED WITH DIELECTRIC FILM FIRST AND STRUCTURES FORMED THEREBY [patent_app_type] => utility [patent_app_number] => 16/413906 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413906
Methods of forming interconnect structures using via holes filled with dielectric film May 15, 2019 Issued
Array ( [id] => 16172903 [patent_doc_number] => 10714481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Semiconductor structure having air gap between gate electrode and distal end portion of active area and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/412447 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 2895 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412447
Semiconductor structure having air gap between gate electrode and distal end portion of active area and fabrication method thereof May 14, 2019 Issued
Array ( [id] => 14786101 [patent_doc_number] => 20190267948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => POWER CONTROL CIRCUIT AND POWER AMPLIFIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/411095 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411095
Power control circuit and power amplifier circuit May 12, 2019 Issued
Array ( [id] => 14813727 [patent_doc_number] => 20190273473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => HIGH-LINEARITY CMOS WIFI RF POWER AMPLIFIERS IN WIDE RANGE OF BURST SIGNALS [patent_app_type] => utility [patent_app_number] => 16/408139 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408139
HIGH-LINEARITY CMOS WIFI RF POWER AMPLIFIERS IN WIDE RANGE OF BURST SIGNALS May 8, 2019 Abandoned
Array ( [id] => 15808943 [patent_doc_number] => 20200127614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => PEAK VOLTAGE LIMITING CIRCUITS AND METHODS FOR POWER AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 16/404739 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404739
PEAK VOLTAGE LIMITING CIRCUITS AND METHODS FOR POWER AMPLIFIERS May 6, 2019 Abandoned
Array ( [id] => 17026132 [patent_doc_number] => 20210250004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => COMPACT HIGH GAIN AMPLIFIER WITH DC COUPLED STAGES [patent_app_type] => utility [patent_app_number] => 17/052800 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17052800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/052800
Compact high gain amplifier with DC coupled stages May 6, 2019 Issued
Array ( [id] => 16425666 [patent_doc_number] => 20200350864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => RF AMPLIFIER HAVING MAXIMUM EFFICIENCY AND SWR PROTECTION FEATURES AND METHODS FOR PROVIDING MAXIMUM EFFICIENCY RF AMPLIFICATION [patent_app_type] => utility [patent_app_number] => 16/404668 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404668
RF amplifier having maximum efficiency and SWR protection features and methods for providing maximum efficiency RF amplification May 5, 2019 Issued
Array ( [id] => 16739591 [patent_doc_number] => 10965264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Bias circuit for supplying a bias current to an RF power amplifier [patent_app_type] => utility [patent_app_number] => 16/402243 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402243
Bias circuit for supplying a bias current to an RF power amplifier May 2, 2019 Issued
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