Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11274360 [patent_doc_number] => 20160336908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ELECTRICAL SIGNAL AMPLIFIER, CIRCUIT ARRANGEMENT AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/155562 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3375 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155562
Electrical signal amplifier, circuit arrangement and method May 15, 2016 Issued
Array ( [id] => 11883831 [patent_doc_number] => 09755015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Air gaps formed by porous silicon removal' [patent_app_type] => utility [patent_app_number] => 15/150977 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2807 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15150977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/150977
Air gaps formed by porous silicon removal May 9, 2016 Issued
Array ( [id] => 11877123 [patent_doc_number] => 09748908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Transimpedance amplifier' [patent_app_type] => utility [patent_app_number] => 15/149281 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3848 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15149281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/149281
Transimpedance amplifier May 8, 2016 Issued
Array ( [id] => 14333093 [patent_doc_number] => 10297575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor device utilizing an adhesive to attach an upper package to a lower die [patent_app_type] => utility [patent_app_number] => 15/148747 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9716 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148747
Semiconductor device utilizing an adhesive to attach an upper package to a lower die May 5, 2016 Issued
Array ( [id] => 11132890 [patent_doc_number] => 20160329866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'RF POWER AMPLIFIERS WITH DIODE LINEARIZER' [patent_app_type] => utility [patent_app_number] => 15/148167 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7344 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148167 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148167
RF power amplifiers with diode linearizer May 5, 2016 Issued
Array ( [id] => 11518160 [patent_doc_number] => 20170085234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'APPARATUS FOR PERFORMING CAPACITOR AMPLIFICATION IN AN ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/147902 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4093 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147902
Apparatus for performing capacitor amplification in an electronic device May 4, 2016 Issued
Array ( [id] => 14366981 [patent_doc_number] => 10304803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Nanoscale interconnect array for stacked dies [patent_app_type] => utility [patent_app_number] => 15/147807 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5289 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147807
Nanoscale interconnect array for stacked dies May 4, 2016 Issued
Array ( [id] => 11940216 [patent_doc_number] => 20170244367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'HIGH LINEARITY INDUCTORLESS LNA' [patent_app_type] => utility [patent_app_number] => 15/144455 [patent_app_country] => US [patent_app_date] => 2016-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15144455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/144455
High linearity inductorless LNA May 1, 2016 Issued
Array ( [id] => 11666131 [patent_doc_number] => 20170154850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'STRUCTURE FOR STACKED LOGIC PERFORMANCE IMPROVEMENT' [patent_app_type] => utility [patent_app_number] => 15/143950 [patent_app_country] => US [patent_app_date] => 2016-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143950 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143950
Structure for stacked logic performance improvement May 1, 2016 Issued
Array ( [id] => 12027067 [patent_doc_number] => 20170317166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'ISOLATION STRUCTURES FOR CIRCUITS SHARING A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/142838 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3430 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142838
ISOLATION STRUCTURES FOR CIRCUITS SHARING A SUBSTRATE Apr 28, 2016 Abandoned
Array ( [id] => 16201168 [patent_doc_number] => 10726337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Method and apparatus for emulation of neuromorphic hardware including neurons and synapses connecting the neurons [patent_app_type] => utility [patent_app_number] => 15/143466 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9444 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143466
Method and apparatus for emulation of neuromorphic hardware including neurons and synapses connecting the neurons Apr 28, 2016 Issued
Array ( [id] => 11817970 [patent_doc_number] => 09721928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Integrated circuit package having two substrates' [patent_app_type] => utility [patent_app_number] => 15/141628 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141628
Integrated circuit package having two substrates Apr 27, 2016 Issued
Array ( [id] => 12802942 [patent_doc_number] => 20180159484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => LINEAR CMOS PA WITH LOW QUIESCENT CURRENT AND BOOSTED MAXIMUM LINEAR OUTPUT POWER [patent_app_type] => utility [patent_app_number] => 15/578058 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15578058 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/578058
Linear CMOS PA with low quiescent current and boosted maximum linear output power Apr 27, 2016 Issued
Array ( [id] => 11925646 [patent_doc_number] => 09793235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Semiconductor package having a bump bonding structure' [patent_app_type] => utility [patent_app_number] => 15/139072 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139072
Semiconductor package having a bump bonding structure Apr 25, 2016 Issued
Array ( [id] => 11111528 [patent_doc_number] => 20160308498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'APPARATUS AND METHOD FOR SELF BIAS IN GALLIUM NITRIDE (GaN) AMPLIFIERS' [patent_app_type] => utility [patent_app_number] => 15/133689 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/133689
Apparatus and method for gallium nitride (GaN) amplifiers Apr 19, 2016 Issued
Array ( [id] => 11036284 [patent_doc_number] => 20160233239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'LIGHT-EMITTING DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/131119 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13589 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131119
Light-emitting display device having oxide semiconductor layer overlapping with adjacent pixel electrode Apr 17, 2016 Issued
Array ( [id] => 11862046 [patent_doc_number] => 09741737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material' [patent_app_type] => utility [patent_app_number] => 15/130803 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130803
Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material Apr 14, 2016 Issued
Array ( [id] => 11911906 [patent_doc_number] => 09780737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Digitally-controlled transimpedance amplifier (TIA) circuit and methods' [patent_app_type] => utility [patent_app_number] => 15/087711 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087711 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087711
Digitally-controlled transimpedance amplifier (TIA) circuit and methods Mar 30, 2016 Issued
Array ( [id] => 14126643 [patent_doc_number] => 10250194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Broadband envelope tracking [patent_app_type] => utility [patent_app_number] => 15/085477 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7548 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085477 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085477
Broadband envelope tracking Mar 29, 2016 Issued
Array ( [id] => 11014248 [patent_doc_number] => 20160211201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'MANUFACTURING AND EVALUATION METHOD OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/081988 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5092 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081988
MANUFACTURING AND EVALUATION METHOD OF A SEMICONDUCTOR DEVICE Mar 27, 2016 Abandoned
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