Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19597011 [patent_doc_number] => 12154865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Power semiconductor device including a semiconductor chip [patent_app_type] => utility [patent_app_number] => 17/673007 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5013 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673007
Power semiconductor device including a semiconductor chip Feb 15, 2022 Issued
Array ( [id] => 18570620 [patent_doc_number] => 20230260957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => ELECTRONIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/670320 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670320
ELECTRONIC STRUCTURE Feb 10, 2022 Pending
Array ( [id] => 18645626 [patent_doc_number] => 11769704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and a post passivation layer disposed on the anti-arcing pattern [patent_app_type] => utility [patent_app_number] => 17/667564 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667564
Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and a post passivation layer disposed on the anti-arcing pattern Feb 8, 2022 Issued
Array ( [id] => 18541489 [patent_doc_number] => 20230246605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => CLASS AB MONTICELLI OUTPUT STAGE DESIGN WITH BIAS TEMPERATURE INSTABILITY TOLERANCE [patent_app_type] => utility [patent_app_number] => 17/589585 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589585
CLASS AB MONTICELLI OUTPUT STAGE DESIGN WITH BIAS TEMPERATURE INSTABILITY TOLERANCE Jan 30, 2022 Pending
Array ( [id] => 18533845 [patent_doc_number] => 20230238922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => LOW-HEADROOM DYNAMIC BASE CURRENT CANCELLATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/586391 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586391
LOW-HEADROOM DYNAMIC BASE CURRENT CANCELLATION TECHNIQUES Jan 26, 2022 Pending
Array ( [id] => 17796422 [patent_doc_number] => 20220255514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => PARALLEL CASCODE AMPLIFIER FOR ENHANCED LOW-POWER MODE EFFICIENCY [patent_app_type] => utility [patent_app_number] => 17/578631 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578631
Parallel cascode amplifier for enhanced low-power mode efficiency Jan 18, 2022 Issued
Array ( [id] => 17709711 [patent_doc_number] => 20220209719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => Drain Switched Split Amplifier with Capacitor Switching for Noise Figure and Isolation Improvement in Split Mode [patent_app_type] => utility [patent_app_number] => 17/573375 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573375
Drain switched split amplifier with capacitor switching for noise figure and isolation improvement in split mode Jan 10, 2022 Issued
Array ( [id] => 17566732 [patent_doc_number] => 20220130881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => IMAGE SENSOR DEVICE HAVING A FIRST LENS AND A SECOND LENS OVER THE FIRST LENS [patent_app_type] => utility [patent_app_number] => 17/571071 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571071 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571071
Image sensor device having a first lens and a second lens over the first lens Jan 6, 2022 Issued
Array ( [id] => 18488485 [patent_doc_number] => 20230215833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => Limiting Failures Caused by Dendrite Growth on Semiconductor Chips [patent_app_type] => utility [patent_app_number] => 17/567322 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567322
Limiting Failures Caused by Dendrite Growth on Semiconductor Chips Jan 2, 2022 Pending
Array ( [id] => 18840175 [patent_doc_number] => 11848254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Method for manufacturing a semiconductor package having a conductive pad with an anchor flange [patent_app_type] => utility [patent_app_number] => 17/646344 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 2627 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646344
Method for manufacturing a semiconductor package having a conductive pad with an anchor flange Dec 28, 2021 Issued
Array ( [id] => 17537384 [patent_doc_number] => 20220115993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => Bandwidth Enhanced Gain Stage with Improved Common Mode Rejection Ratio [patent_app_type] => utility [patent_app_number] => 17/645834 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645834
Bandwidth Enhanced Gain Stage with Improved Common Mode Rejection Ratio Dec 22, 2021 Pending
Array ( [id] => 18623721 [patent_doc_number] => 11756776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Amplifier [patent_app_type] => utility [patent_app_number] => 17/553171 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 16564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553171
Amplifier Dec 15, 2021 Issued
Array ( [id] => 19356915 [patent_doc_number] => 12057372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Methods for forming contact structures and semiconductor devices including forming a spacer structure into a base structure [patent_app_type] => utility [patent_app_number] => 17/549557 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549557
Methods for forming contact structures and semiconductor devices including forming a spacer structure into a base structure Dec 12, 2021 Issued
Array ( [id] => 18357893 [patent_doc_number] => 11646299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Method of manufacturing a semiconductor package including a first sub-package stacked atop a second sub-package [patent_app_type] => utility [patent_app_number] => 17/643593 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4476 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643593
Method of manufacturing a semiconductor package including a first sub-package stacked atop a second sub-package Dec 9, 2021 Issued
Array ( [id] => 18875313 [patent_doc_number] => 11863139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Amplifier and receiving circuit, semiconductor apparatus, and semiconductor system using the same [patent_app_type] => utility [patent_app_number] => 17/544478 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9391 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544478
Amplifier and receiving circuit, semiconductor apparatus, and semiconductor system using the same Dec 6, 2021 Issued
Array ( [id] => 17963647 [patent_doc_number] => 20220344228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => Power Semiconductor Package Unit of Surface Mount Technology and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 17/543872 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543872
Power semiconductor package unit of surface mount technology including a plastic film covering a chip Dec 6, 2021 Issued
Array ( [id] => 17509187 [patent_doc_number] => 20220102290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/643176 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643176
Method of forming a semiconductor structure including forming a buffer structure over a metal layer Dec 6, 2021 Issued
Array ( [id] => 19428300 [patent_doc_number] => 12087734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method for forming chip packages and a chip package having a chipset comprising a first chip and a second chip [patent_app_type] => utility [patent_app_number] => 17/542415 [patent_app_country] => US [patent_app_date] => 2021-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 6461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542415
Method for forming chip packages and a chip package having a chipset comprising a first chip and a second chip Dec 3, 2021 Issued
Array ( [id] => 18061757 [patent_doc_number] => 20220392844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/535887 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535887
Semiconductor package including an interposer disposed on a package substrate and a capping structure disposed on the interposer Nov 25, 2021 Issued
Array ( [id] => 19414860 [patent_doc_number] => 12080697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method for forming a three-dimensional (3D) memory device having bonded semiconductor structures [patent_app_type] => utility [patent_app_number] => 17/525533 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 27310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525533
Method for forming a three-dimensional (3D) memory device having bonded semiconductor structures Nov 11, 2021 Issued
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