
Mohammad M. Ali
Examiner (ID: 3439, Phone: (571)272-4806 , Office: P/3744 )
| Most Active Art Unit | 3744 |
| Art Unit(s) | 3784, 3744 |
| Total Applications | 2900 |
| Issued Applications | 2338 |
| Pending Applications | 41 |
| Abandoned Applications | 530 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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