Search

Mohammad M Ali

Examiner (ID: 9935, Phone: (571)272-4806 , Office: P/3744 )

Most Active Art Unit
3744
Art Unit(s)
3784, 3744
Total Applications
2900
Issued Applications
2328
Pending Applications
41
Abandoned Applications
531

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19199554 [patent_doc_number] => 11996811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Power amplifier circuit [patent_app_type] => utility [patent_app_number] => 17/341953 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341953
Power amplifier circuit Jun 7, 2021 Issued
Array ( [id] => 18494236 [patent_doc_number] => 11699657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layer [patent_app_type] => utility [patent_app_number] => 17/340596 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 11412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340596
Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layer Jun 6, 2021 Issued
Array ( [id] => 19583080 [patent_doc_number] => 12149213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Wideband multi gain LNA architecture [patent_app_type] => utility [patent_app_number] => 17/337227 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9135 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337227
Wideband multi gain LNA architecture Jun 1, 2021 Issued
Array ( [id] => 19138074 [patent_doc_number] => 11973050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Method for forming an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance [patent_app_type] => utility [patent_app_number] => 17/336888 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 10671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336888
Method for forming an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance Jun 1, 2021 Issued
Array ( [id] => 17263814 [patent_doc_number] => 20210376799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => CONTROL CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/333649 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333649
CONTROL CIRCUIT May 27, 2021 Pending
Array ( [id] => 17536685 [patent_doc_number] => 20220115294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/331951 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331951
Semiconductor device having a stack including electrodes vertically stacked on a substrate and electronic system including the same May 26, 2021 Issued
Array ( [id] => 18641250 [patent_doc_number] => 11765893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Structure of memory device having floating gate with protruding structure [patent_app_type] => utility [patent_app_number] => 17/331319 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331319
Structure of memory device having floating gate with protruding structure May 25, 2021 Issued
Array ( [id] => 17085526 [patent_doc_number] => 20210280533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => CRACK SUPPRESSION STRUCTURE FOR HV ISOLATION COMPONENT [patent_app_type] => utility [patent_app_number] => 17/329314 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329314
CRACK SUPPRESSION STRUCTURE FOR HV ISOLATION COMPONENT May 24, 2021 Pending
Array ( [id] => 18875303 [patent_doc_number] => 11863129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Bias circuit [patent_app_type] => utility [patent_app_number] => 17/328473 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 497 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328473
Bias circuit May 23, 2021 Issued
Array ( [id] => 17071396 [patent_doc_number] => 20210273613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => AMPLIFICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/325350 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325350
Amplification circuit May 19, 2021 Issued
Array ( [id] => 19063644 [patent_doc_number] => 11942907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Amplifier [patent_app_type] => utility [patent_app_number] => 17/322222 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13328 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322222 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322222
Amplifier May 16, 2021 Issued
Array ( [id] => 19552892 [patent_doc_number] => 12136605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/320767 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8476 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320767
Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same May 13, 2021 Issued
Array ( [id] => 17145287 [patent_doc_number] => 20210313300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/320759 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320759
Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof May 13, 2021 Issued
Array ( [id] => 18827645 [patent_doc_number] => 11842935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Method for forming a reconstructed package substrate comprising substrates blocks [patent_app_type] => utility [patent_app_number] => 17/318703 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 6602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318703
Method for forming a reconstructed package substrate comprising substrates blocks May 11, 2021 Issued
Array ( [id] => 19109160 [patent_doc_number] => 11962278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Programmable baseband filter for selectively coupling with at least a portion of another filter [patent_app_type] => utility [patent_app_number] => 17/318959 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 15161 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318959
Programmable baseband filter for selectively coupling with at least a portion of another filter May 11, 2021 Issued
Array ( [id] => 19244648 [patent_doc_number] => 12015103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Micro light emitting diode display panel with option of choosing to emit light both or respectively of light-emitting regions [patent_app_type] => utility [patent_app_number] => 17/315366 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 9223 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315366
Micro light emitting diode display panel with option of choosing to emit light both or respectively of light-emitting regions May 9, 2021 Issued
Array ( [id] => 17233100 [patent_doc_number] => 20210359657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => AUTOMATIC GAIN CONTROL CIRCUIT, CORRESPONDING RECEIVER, TRANSMITTER AND METHOD [patent_app_type] => utility [patent_app_number] => 17/314905 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314905
AUTOMATIC GAIN CONTROL CIRCUIT, CORRESPONDING RECEIVER, TRANSMITTER AND METHOD May 6, 2021 Pending
Array ( [id] => 17040751 [patent_doc_number] => 20210257387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures [patent_app_type] => utility [patent_app_number] => 17/308766 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308766
Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material May 4, 2021 Issued
Array ( [id] => 19357067 [patent_doc_number] => 12057526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Display device having a first bank defining light emission regions and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/306385 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14202 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306385
Display device having a first bank defining light emission regions and method of manufacturing the same May 2, 2021 Issued
Array ( [id] => 17986023 [patent_doc_number] => 20220352060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => STACKED VIA STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/243600 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243600
Stacked via structure disposed on a conductive pillar of a semiconductor die Apr 28, 2021 Issued
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