Search

Mohammad M. Choudhry

Examiner (ID: 10423, Phone: (571)270-5716 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2898, 4126, 2899, 2894
Total Applications
890
Issued Applications
699
Pending Applications
82
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17389497 [patent_doc_number] => 20220037349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => COMPACT MEMORY CELL WITH A SHARED CONDUCTIVE SELECT GATE AND METHODS OF MAKING SUCH A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/940586 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940586
Compact memory cell with a shared conductive select gate and methods of making such a memory cell Jul 27, 2020 Issued
Array ( [id] => 16601544 [patent_doc_number] => 20210028075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => SUBSTRATE PROCESSING MONITORING [patent_app_type] => utility [patent_app_number] => 16/938510 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938510
Substrate processing monitoring Jul 23, 2020 Issued
Array ( [id] => 16601650 [patent_doc_number] => 20210028181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/936401 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936401 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936401
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Jul 21, 2020 Abandoned
Array ( [id] => 16578823 [patent_doc_number] => 20210013224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STRINGS [patent_app_type] => utility [patent_app_number] => 16/924531 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924531
Process for a 3-dimensional array of horizontal NOR-type memory strings Jul 8, 2020 Issued
Array ( [id] => 16530713 [patent_doc_number] => 20200404794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/923765 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923765
Semiconductor device Jul 7, 2020 Issued
Array ( [id] => 18857344 [patent_doc_number] => 11854939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Three-dimensional integrated system of dram chip and preparation method thereof [patent_app_type] => utility [patent_app_number] => 17/052861 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3339 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17052861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/052861
Three-dimensional integrated system of dram chip and preparation method thereof Jul 1, 2020 Issued
Array ( [id] => 16677361 [patent_doc_number] => 20210066127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/904659 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904659
Method for manufacturing an electronic device Jun 17, 2020 Issued
Array ( [id] => 16944202 [patent_doc_number] => 11056453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Stackable fully molded semiconductor structure with vertical interconnects [patent_app_type] => utility [patent_app_number] => 16/904404 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 12857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904404
Stackable fully molded semiconductor structure with vertical interconnects Jun 16, 2020 Issued
Array ( [id] => 17700183 [patent_doc_number] => 11373916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Method and apparatus [patent_app_type] => utility [patent_app_number] => 16/899439 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899439
Method and apparatus Jun 10, 2020 Issued
Array ( [id] => 16692242 [patent_doc_number] => 20210074721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/897836 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897836
SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME Jun 9, 2020 Abandoned
Array ( [id] => 16905077 [patent_doc_number] => 20210183993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => FILM STRUCTURE INCLUDING HAFNIUM OXIDE, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/895362 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895362
Film structure including hafnium oxide, electronic device including the same, and method of manufacturing the same Jun 7, 2020 Issued
Array ( [id] => 16316193 [patent_doc_number] => 20200294931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/886168 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886168
Method of manufacturing semiconductor device May 27, 2020 Issued
Array ( [id] => 17745650 [patent_doc_number] => 11393732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Method for testing electrical performance of packaged chip [patent_app_type] => utility [patent_app_number] => 17/272766 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3448 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17272766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/272766
Method for testing electrical performance of packaged chip May 14, 2020 Issued
Array ( [id] => 19063132 [patent_doc_number] => 11942382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor device and method for manufacturing semiconductor element [patent_app_type] => utility [patent_app_number] => 16/874488 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5696 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874488 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874488
Semiconductor device and method for manufacturing semiconductor element May 13, 2020 Issued
Array ( [id] => 18766895 [patent_doc_number] => 11817304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Method of manufacturing microelectronic devices, related devices, systems, and apparatus [patent_app_type] => utility [patent_app_number] => 16/871266 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871266
Method of manufacturing microelectronic devices, related devices, systems, and apparatus May 10, 2020 Issued
Array ( [id] => 16966357 [patent_doc_number] => 20210217856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => CHANNEL STRUCTURE HAVING TUNNELING LAYER WITH ADJUSTED NITROGEN WEIGHT PERCENT AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/860971 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860971
Channel structure having tunneling layer with adjusted nitrogen weight percent and methods for forming the same Apr 27, 2020 Issued
Array ( [id] => 17289100 [patent_doc_number] => 11205661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Three-dimensional memory devices with enlarged joint critical dimension and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/860890 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860890
Three-dimensional memory devices with enlarged joint critical dimension and methods for forming the same Apr 27, 2020 Issued
Array ( [id] => 18105508 [patent_doc_number] => 11545405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Packaging for fingerprint sensors and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/857907 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 5948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/857907
Packaging for fingerprint sensors and methods of manufacture Apr 23, 2020 Issued
Array ( [id] => 17708237 [patent_doc_number] => 20220208245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/604523 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17604523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/604523
Semiconductor device and electronic device Apr 12, 2020 Issued
Array ( [id] => 19183780 [patent_doc_number] => 11990380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Methods and systems for combining x-ray metrology data sets to improve parameter estimation [patent_app_type] => utility [patent_app_number] => 16/847388 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 10989 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847388
Methods and systems for combining x-ray metrology data sets to improve parameter estimation Apr 12, 2020 Issued
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