Search

Mohammad M. Choudhry

Examiner (ID: 10423, Phone: (571)270-5716 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2898, 4126, 2899, 2894
Total Applications
890
Issued Applications
699
Pending Applications
82
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11983759 [patent_doc_number] => 20170287914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Method and Apparatus for Forming Boron-Doped Silicon Germanium Film, and Storage Medium' [patent_app_type] => utility [patent_app_number] => 15/472486 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472486
Method and apparatus for forming boron-doped silicon germanium film, and storage medium Mar 28, 2017 Issued
Array ( [id] => 13470241 [patent_doc_number] => 20180286663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => METHOD OF REFORMING INSULATING FILM DEPOSITED ON SUBSTRATE WITH RECESS PATTERN [patent_app_type] => utility [patent_app_number] => 15/472750 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472750
Method of reforming insulating film deposited on substrate with recess pattern Mar 28, 2017 Issued
Array ( [id] => 12102024 [patent_doc_number] => 09859123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/472308 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472308
Method for fabricating semiconductor device Mar 28, 2017 Issued
Array ( [id] => 14205035 [patent_doc_number] => 10269639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Method of manufacturing packaged wafer [patent_app_type] => utility [patent_app_number] => 15/472995 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5188 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472995
Method of manufacturing packaged wafer Mar 28, 2017 Issued
Array ( [id] => 14252501 [patent_doc_number] => 10276457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Method for measuring charge accumulation in fabrication process of semiconductor device and method for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/472306 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5121 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472306
Method for measuring charge accumulation in fabrication process of semiconductor device and method for fabricating semiconductor device Mar 28, 2017 Issued
Array ( [id] => 13159463 [patent_doc_number] => 10096465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Substrate processing method, substrate processing apparatus and recording medium [patent_app_type] => utility [patent_app_number] => 15/471360 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 6317 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471360
Substrate processing method, substrate processing apparatus and recording medium Mar 27, 2017 Issued
Array ( [id] => 12215096 [patent_doc_number] => 09911914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-06 [patent_title] => 'Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices' [patent_app_type] => utility [patent_app_number] => 15/471497 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 5840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471497
Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices Mar 27, 2017 Issued
Array ( [id] => 13452161 [patent_doc_number] => 20180277623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SURFACE AREA ENHANCEMENT FOR STACKED METAL-INSULATOR-METAL (MIM) CAPACITOR [patent_app_type] => utility [patent_app_number] => 15/469860 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469860
Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor Mar 26, 2017 Issued
Array ( [id] => 11730729 [patent_doc_number] => 20170192172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'INTEGRATION OF PHOTONIC, ELECTRONIC, AND SENSOR DEVICES WITH SOI VLSI MICROPROCESSOR TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 15/466966 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466966 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/466966
Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology Mar 22, 2017 Issued
Array ( [id] => 13951037 [patent_doc_number] => 10211300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Method of forming a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/452769 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 12169 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452769
Method of forming a semiconductor device Mar 7, 2017 Issued
Array ( [id] => 11990193 [patent_doc_number] => 20170294348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'METHODS FOR FORMING 2-DIMENSIONAL SELF-ALIGNED VIAS' [patent_app_type] => utility [patent_app_number] => 15/453675 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453675 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453675
Methods for forming 2-dimensional self-aligned vias Mar 7, 2017 Issued
Array ( [id] => 14093907 [patent_doc_number] => 10242866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Selective deposition of silicon nitride on silicon oxide using catalytic control [patent_app_type] => utility [patent_app_number] => 15/453815 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453815
Selective deposition of silicon nitride on silicon oxide using catalytic control Mar 7, 2017 Issued
Array ( [id] => 12109193 [patent_doc_number] => 09865681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'Nanowire transistors having multiple threshold voltages' [patent_app_type] => utility [patent_app_number] => 15/453170 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453170
Nanowire transistors having multiple threshold voltages Mar 7, 2017 Issued
Array ( [id] => 13271039 [patent_doc_number] => 10147606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Methods of forming semiconductor device structures including linear structures substantially aligned with other structures [patent_app_type] => utility [patent_app_number] => 15/452467 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 22123 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452467
Methods of forming semiconductor device structures including linear structures substantially aligned with other structures Mar 6, 2017 Issued
Array ( [id] => 14268271 [patent_doc_number] => 10283708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Methods and apparatus for three-dimensional nonvolatile memory [patent_app_type] => utility [patent_app_number] => 15/452373 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 11618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452373 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452373
Methods and apparatus for three-dimensional nonvolatile memory Mar 6, 2017 Issued
Array ( [id] => 13419915 [patent_doc_number] => 20180261500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SELECTIVE PORESEAL DEPOSITION PREVENTION AND RESIDUE REMOVAL USING SAM [patent_app_type] => utility [patent_app_number] => 15/452394 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452394
Selective poreseal deposition prevention and residue removal using SAM Mar 6, 2017 Issued
Array ( [id] => 12174779 [patent_doc_number] => 09892927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'System and method for mitigating oxide growth in a gate dielectric' [patent_app_type] => utility [patent_app_number] => 15/443151 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6463 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443151
System and method for mitigating oxide growth in a gate dielectric Feb 26, 2017 Issued
Array ( [id] => 11674064 [patent_doc_number] => 20170162787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'RRAM CELL BOTTOM ELECTRODE FORMATION' [patent_app_type] => utility [patent_app_number] => 15/433353 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433353
RRAM cell bottom electrode formation Feb 14, 2017 Issued
Array ( [id] => 11652995 [patent_doc_number] => 20170148896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE OF A MULTIGATE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/426566 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426566
Fabrication process for mitigating external resistance of a multigate device Feb 6, 2017 Issued
Array ( [id] => 16479551 [patent_doc_number] => 10854505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Removing polymer through treatment [patent_app_type] => utility [patent_app_number] => 15/405391 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405391 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405391
Removing polymer through treatment Jan 12, 2017 Issued
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