Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18721640 [patent_doc_number] => 11798997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/471628 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9962 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471628
Semiconductor device Sep 9, 2021 Issued
Array ( [id] => 17738145 [patent_doc_number] => 20220223607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/470948 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470948
SEMICONDUCTOR MEMORY DEVICE Sep 8, 2021 Abandoned
Array ( [id] => 18239994 [patent_doc_number] => 20230072305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => Vertical Transistor with Late Source/Drain Epitaxy [patent_app_type] => utility [patent_app_number] => 17/470686 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470686
Vertical transistor with late source/drain epitaxy Sep 8, 2021 Issued
Array ( [id] => 17886829 [patent_doc_number] => 20220302307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/470626 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470626
Semiconductor device including energy level in drift layer Sep 8, 2021 Issued
Array ( [id] => 17402849 [patent_doc_number] => 20220044940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/468804 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468804
Semiconductor structure and manufacturing method thereof Sep 7, 2021 Issued
Array ( [id] => 17708771 [patent_doc_number] => 20220208779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE, NONVOLATILE MEMORY DEVICE INCLUDING THE SAME, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/468917 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468917
Semiconductor device, including element isolation layer and nonvolatile memory device including the same Sep 7, 2021 Issued
Array ( [id] => 18223972 [patent_doc_number] => 20230062966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/800248 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17800248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/800248
Display panel including power connection lines and display device Sep 6, 2021 Issued
Array ( [id] => 18223825 [patent_doc_number] => 20230062819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => COMPLEMENTARY FET (CFET) BURIED SIDEWALL CONTACT WITH SPACER FOOT [patent_app_type] => utility [patent_app_number] => 17/463704 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463704
Complementary FET (CFET) buried sidewall contact with spacer foot Aug 31, 2021 Issued
Array ( [id] => 19741404 [patent_doc_number] => 12218252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor structure with source and drain electrode embedded within semiconductor layer and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/460969 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460969
Semiconductor structure with source and drain electrode embedded within semiconductor layer and manufacturing method thereof Aug 29, 2021 Issued
Array ( [id] => 20347606 [patent_doc_number] => 12471344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Dry etching of semiconductor structures with fluorine-containing gases [patent_app_type] => utility [patent_app_number] => 17/461186 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461186
Dry etching of semiconductor structures with fluorine-containing gases Aug 29, 2021 Issued
Array ( [id] => 17295491 [patent_doc_number] => 20210391330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SEMICONDUCTOR STRUCTURE AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/460414 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460414
Method for forming semiconductor structure by using sacrificial layer configured to be replaced subsequently to form bit line, semiconductor structure, and memory Aug 29, 2021 Issued
Array ( [id] => 18228994 [patent_doc_number] => 20230067988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ISOLATION STRUCTURES IN MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/460620 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460620 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460620
Isolation structures in multi-gate semiconductor devices and methods of fabricating the same Aug 29, 2021 Issued
Array ( [id] => 18225641 [patent_doc_number] => 20230064635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Semiconductor Device With Low Resistances and Methods of Forming Such [patent_app_type] => utility [patent_app_number] => 17/460847 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460847
Semiconductor device with low resistances and methods of forming such Aug 29, 2021 Issued
Array ( [id] => 19341430 [patent_doc_number] => 12051626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Fin Field-Effect transistor and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/460106 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460106
Fin Field-Effect transistor and method of forming the same Aug 26, 2021 Issued
Array ( [id] => 20531895 [patent_doc_number] => 12550346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Reverse-conducting IGBT chip [patent_app_type] => utility [patent_app_number] => 18/022499 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4605 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18022499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/022499
Reverse-conducting IGBT chip Aug 22, 2021 Issued
Array ( [id] => 17752930 [patent_doc_number] => 20220231135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/399318 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399318
Semiconductor device having multiple conductive members Aug 10, 2021 Issued
Array ( [id] => 18913137 [patent_doc_number] => 11876126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/398037 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 115 [patent_no_of_words] => 38701 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398037
Method for manufacturing semiconductor device Aug 9, 2021 Issued
Array ( [id] => 17431985 [patent_doc_number] => 20220059694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => INTEGRATED CIRCUIT MEMORY AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/389898 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389898
Integrated circuit memory and manufacturing method thereof, and semiconductor integrated circuit device Jul 29, 2021 Issued
Array ( [id] => 18164977 [patent_doc_number] => 20230031574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MOON-SHAPED BOTTOM SPACER FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR (VTFET) DEVICES [patent_app_type] => utility [patent_app_number] => 17/388572 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388572
Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices Jul 28, 2021 Issued
Array ( [id] => 18639633 [patent_doc_number] => 11764259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Vertical field-effect transistor with dielectric fin extension [patent_app_type] => utility [patent_app_number] => 17/384307 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 5808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384307
Vertical field-effect transistor with dielectric fin extension Jul 22, 2021 Issued
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