Search

Mohammad M. Hoque

Examiner (ID: 15299, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
845
Issued Applications
653
Pending Applications
101
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18158007 [patent_doc_number] => 20230024598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 17/757516 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/757516
SEMICONDUCTOR ELEMENT Dec 13, 2020 Pending
Array ( [id] => 16812101 [patent_doc_number] => 20210134656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Patterning Methods for Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/119692 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119692
Patterning methods for semiconductor devices Dec 10, 2020 Issued
Array ( [id] => 18001073 [patent_doc_number] => 11502184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor device with spacer of gradually changed thickness and manufacturing method thereof, and electronic device including the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/112762 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8135 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112762
Semiconductor device with spacer of gradually changed thickness and manufacturing method thereof, and electronic device including the semiconductor device Dec 3, 2020 Issued
Array ( [id] => 18073901 [patent_doc_number] => 11532743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Semiconductor device with U-shaped channel and manufacturing method thereof, and electronic apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/110630 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 8335 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110630
Semiconductor device with U-shaped channel and manufacturing method thereof, and electronic apparatus including the same Dec 2, 2020 Issued
Array ( [id] => 16889132 [patent_doc_number] => 20210175329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE BIPOLAR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/106413 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106413
Semiconductor device including an anode contact region having a varied doping concentration Nov 29, 2020 Issued
Array ( [id] => 16752616 [patent_doc_number] => 20210104628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 17/102819 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102819
Semiconductor device having semiconductor pillar with first impurity region formed lower part of the pillar and second impurity region formed upper part of the pillar Nov 23, 2020 Issued
Array ( [id] => 18073665 [patent_doc_number] => 11532503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Conductive feature structure including a blocking region [patent_app_type] => utility [patent_app_number] => 17/101858 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101858
Conductive feature structure including a blocking region Nov 22, 2020 Issued
Array ( [id] => 18120791 [patent_doc_number] => 11552190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region [patent_app_type] => utility [patent_app_number] => 16/952500 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5925 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952500
High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region Nov 18, 2020 Issued
Array ( [id] => 17615671 [patent_doc_number] => 20220157951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDCUTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/950586 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950586
HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDCUTOR DEVICES AND MANUFACTURING METHOD THEREOF Nov 16, 2020 Abandoned
Array ( [id] => 16677524 [patent_doc_number] => 20210066290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Fin Structure and Method of Forming Same Through Two-Step Etching Processes [patent_app_type] => utility [patent_app_number] => 17/097423 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097423
Fin structure and method of forming same through two-step etching processes Nov 12, 2020 Issued
Array ( [id] => 18563167 [patent_doc_number] => 11728422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/096697 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7887 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096697
Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof Nov 11, 2020 Issued
Array ( [id] => 17599610 [patent_doc_number] => 20220149184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => VERTICAL RECONFIGURABLE FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/093716 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093716
Vertical reconfigurable field effect transistor Nov 9, 2020 Issued
Array ( [id] => 18540954 [patent_doc_number] => 20230246066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR SUPER-JUNCTION DEVICE [patent_app_type] => utility [patent_app_number] => 17/621486 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17621486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/621486
Manufacturing method of semiconductor super-junction device Nov 9, 2020 Issued
Array ( [id] => 16812434 [patent_doc_number] => 20210134989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/086358 [patent_app_country] => US [patent_app_date] => 2020-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086358
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF Oct 30, 2020 Abandoned
Array ( [id] => 17509357 [patent_doc_number] => 20220102460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Display Substrate and Manufacturing Method Therefor, and Display Device [patent_app_type] => utility [patent_app_number] => 17/298032 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17298032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/298032
Display substrate and manufacturing method therefor, and display device Oct 27, 2020 Issued
Array ( [id] => 17915112 [patent_doc_number] => 20220317508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/310374 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310374
Display substrate with a bonding pad including conductive parts in different layers and method for manufacturing the same, display device Oct 22, 2020 Issued
Array ( [id] => 17070836 [patent_doc_number] => 20210273053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/069990 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069990
Semiconductor device including first and second buffer layers Oct 13, 2020 Issued
Array ( [id] => 16625011 [patent_doc_number] => 20210043664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR IMAGE SENSOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/069665 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069665
Method for manufacturing semiconductor image sensor device having deep trench isolation Oct 12, 2020 Issued
Array ( [id] => 17523221 [patent_doc_number] => 20220109070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/063182 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063182
HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH VERTICAL CURRENT PATHS AND METHOD OF MAKING THE SAME Oct 4, 2020 Abandoned
Array ( [id] => 18054223 [patent_doc_number] => 11527618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Up-diffusion suppression in a power MOSFET [patent_app_type] => utility [patent_app_number] => 16/948806 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948806
Up-diffusion suppression in a power MOSFET Sep 30, 2020 Issued
Menu