
Mohammad M. Hoque
Examiner (ID: 20, Phone: (571)272-6266 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2823, 2817 |
| Total Applications | 847 |
| Issued Applications | 653 |
| Pending Applications | 102 |
| Abandoned Applications | 113 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17772593
[patent_doc_number] => 11404547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-02
[patent_title] => Semiconductor device with conductive members that extend from a semiconductor portion to an upper surface of a semiconductor layer
[patent_app_type] => utility
[patent_app_number] => 16/807030
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5122
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 318
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807030
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807030 | Semiconductor device with conductive members that extend from a semiconductor portion to an upper surface of a semiconductor layer | Mar 1, 2020 | Issued |
Array
(
[id] => 17825907
[patent_doc_number] => 11430862
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-30
[patent_title] => Superjunction semiconductor device including parallel PN structures and method of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 16/807140
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 10955
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 530
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807140
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807140 | Superjunction semiconductor device including parallel PN structures and method of manufacturing thereof | Mar 1, 2020 | Issued |
Array
(
[id] => 17070860
[patent_doc_number] => 20210273077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-02
[patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE AND DRAIN TOP JUNCTION
[patent_app_type] => utility
[patent_app_number] => 16/805346
[patent_app_country] => US
[patent_app_date] => 2020-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6634
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805346
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/805346 | Vertical field effect transistor with self-aligned source and drain top junction | Feb 27, 2020 | Issued |
Array
(
[id] => 18024645
[patent_doc_number] => 20220376144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => LIGHT-EMITTING DIODE AND DISPLAY DEVICE COMPRISING SAME
[patent_app_type] => utility
[patent_app_number] => 17/636218
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23500
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/636218 | LIGHT-EMITTING DIODE AND DISPLAY DEVICE COMPRISING SAME | Feb 26, 2020 | Pending |
Array
(
[id] => 16286341
[patent_doc_number] => 20200279943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-03
[patent_title] => DUAL SILICIDE WRAP-AROUND CONTACTS FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/803995
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803995
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/803995 | DUAL SILICIDE WRAP-AROUND CONTACTS FOR SEMICONDUCTOR DEVICES | Feb 26, 2020 | Abandoned |
Array
(
[id] => 16020983
[patent_doc_number] => 20200185335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-11
[patent_title] => Method of Manufacturing a Semiconductor Device with Epitaxial Layers and an Alignment Mark
[patent_app_type] => utility
[patent_app_number] => 16/794363
[patent_app_country] => US
[patent_app_date] => 2020-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794363
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/794363 | Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark | Feb 18, 2020 | Issued |
Array
(
[id] => 16973605
[patent_doc_number] => 11069585
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Semiconductor substrate crack mitigation systems and related methods
[patent_app_type] => utility
[patent_app_number] => 16/784687
[patent_app_country] => US
[patent_app_date] => 2020-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4598
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784687
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/784687 | Semiconductor substrate crack mitigation systems and related methods | Feb 6, 2020 | Issued |
Array
(
[id] => 16936451
[patent_doc_number] => 20210202340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/780639
[patent_app_country] => US
[patent_app_date] => 2020-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3413
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780639
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/780639 | Semiconductor device package structure and method for fabricating the same | Feb 2, 2020 | Issued |
Array
(
[id] => 17032971
[patent_doc_number] => 11094791
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-08-17
[patent_title] => Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices
[patent_app_type] => utility
[patent_app_number] => 16/776711
[patent_app_country] => US
[patent_app_date] => 2020-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 5767
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776711
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/776711 | Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices | Jan 29, 2020 | Issued |
Array
(
[id] => 15939211
[patent_doc_number] => 20200161239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => BACK END OF LINE ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATION
[patent_app_type] => utility
[patent_app_number] => 16/751465
[patent_app_country] => US
[patent_app_date] => 2020-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10491
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751465
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/751465 | Back end of line electrical fuse structure and method of fabrication | Jan 23, 2020 | Issued |
Array
(
[id] => 17795758
[patent_doc_number] => 20220254850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/612111
[patent_app_country] => US
[patent_app_date] => 2020-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6753
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17612111
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/612111 | Display device with asymmetric insulating pattern | Jan 16, 2020 | Issued |
Array
(
[id] => 19371684
[patent_doc_number] => 12063789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Scandium nitride magnetic tunnel junction device
[patent_app_type] => utility
[patent_app_number] => 17/422488
[patent_app_country] => US
[patent_app_date] => 2020-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 8584
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17422488
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/422488 | Scandium nitride magnetic tunnel junction device | Jan 15, 2020 | Issued |
Array
(
[id] => 18277044
[patent_doc_number] => 11615992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Substrate isolated VTFET devices
[patent_app_type] => utility
[patent_app_number] => 16/743922
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 6934
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743922
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/743922 | Substrate isolated VTFET devices | Jan 14, 2020 | Issued |
Array
(
[id] => 17107396
[patent_doc_number] => 11127622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-21
[patent_title] => Deep trench isolation and substrate connection on SOI
[patent_app_type] => utility
[patent_app_number] => 16/741011
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 4299
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741011
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741011 | Deep trench isolation and substrate connection on SOI | Jan 12, 2020 | Issued |
Array
(
[id] => 16966155
[patent_doc_number] => 20210217654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => NANOSHEET TRANSISTOR WITH SELF-ALIGNED DIELECTRIC PILLAR
[patent_app_type] => utility
[patent_app_number] => 16/740954
[patent_app_country] => US
[patent_app_date] => 2020-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16740954
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/740954 | Nanosheet transistor with self-aligned dielectric pillar | Jan 12, 2020 | Issued |
Array
(
[id] => 16966390
[patent_doc_number] => 20210217889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH BOTTOM SPACER
[patent_app_type] => utility
[patent_app_number] => 16/738152
[patent_app_country] => US
[patent_app_date] => 2020-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5970
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738152
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/738152 | Vertical field effect transistor with bottom spacer | Jan 8, 2020 | Issued |
Array
(
[id] => 17353292
[patent_doc_number] => 11227939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-18
[patent_title] => Semiconductor structure with grooves and forming method thereof
[patent_app_type] => utility
[patent_app_number] => 16/736921
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4983
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 442
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/736921 | Semiconductor structure with grooves and forming method thereof | Jan 7, 2020 | Issued |
Array
(
[id] => 16896269
[patent_doc_number] => 11037831
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Gate structure and method
[patent_app_type] => utility
[patent_app_number] => 16/737447
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 38
[patent_no_of_words] => 6916
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737447
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737447 | Gate structure and method | Jan 7, 2020 | Issued |
Array
(
[id] => 17424482
[patent_doc_number] => 11257946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Method of forming a power semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/737130
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 37
[patent_no_of_words] => 8736
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737130
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737130 | Method of forming a power semiconductor device | Jan 7, 2020 | Issued |
Array
(
[id] => 15873353
[patent_doc_number] => 20200144080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => SEMICONDUCTOR PACKAGE COMPRISING MOLDING COMPOUND HAVING EXTENDED PORTION AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/734421
[patent_app_country] => US
[patent_app_date] => 2020-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8947
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734421
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/734421 | Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package | Jan 5, 2020 | Issued |