Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16896269 [patent_doc_number] => 11037831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Gate structure and method [patent_app_type] => utility [patent_app_number] => 16/737447 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 6916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737447
Gate structure and method Jan 7, 2020 Issued
Array ( [id] => 17353292 [patent_doc_number] => 11227939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Semiconductor structure with grooves and forming method thereof [patent_app_type] => utility [patent_app_number] => 16/736921 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4983 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736921
Semiconductor structure with grooves and forming method thereof Jan 7, 2020 Issued
Array ( [id] => 15873353 [patent_doc_number] => 20200144080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => SEMICONDUCTOR PACKAGE COMPRISING MOLDING COMPOUND HAVING EXTENDED PORTION AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/734421 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734421
Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package Jan 5, 2020 Issued
Array ( [id] => 17886830 [patent_doc_number] => 20220302308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => TRENCH FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD FOR SAME [patent_app_type] => utility [patent_app_number] => 17/600113 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17600113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/600113
Trench field effect transistor structure free from contact hole Dec 30, 2019 Issued
Array ( [id] => 15873781 [patent_doc_number] => 20200144294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Semiconductor Circuit with Metal Structure and Manufacturing Method [patent_app_type] => utility [patent_app_number] => 16/728033 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728033
Semiconductor circuit with metal structure having different pitches Dec 26, 2019 Issued
Array ( [id] => 19912527 [patent_doc_number] => 12288746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Skip level vias in metallization layers for integrated circuit devices [patent_app_type] => utility [patent_app_number] => 16/727747 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 3338 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727747
Skip level vias in metallization layers for integrated circuit devices Dec 25, 2019 Issued
Array ( [id] => 17500864 [patent_doc_number] => 11289574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Methods of forming epitaxial source/drain features in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/727766 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 5400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727766
Methods of forming epitaxial source/drain features in semiconductor devices Dec 25, 2019 Issued
Array ( [id] => 16120179 [patent_doc_number] => 20200212112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => LIGHTING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/726599 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726599
Lighting apparatus Dec 23, 2019 Issued
Array ( [id] => 16521683 [patent_doc_number] => 10872909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Transistor display panel having an auxiliary layer overlapping portions of source and gate electrodes [patent_app_type] => utility [patent_app_number] => 16/725958 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6562 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725958
Transistor display panel having an auxiliary layer overlapping portions of source and gate electrodes Dec 22, 2019 Issued
Array ( [id] => 17788060 [patent_doc_number] => 11411199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Display panel including multiple areas with a separator disposed therebetween [patent_app_type] => utility [patent_app_number] => 16/722060 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 14968 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722060
Display panel including multiple areas with a separator disposed therebetween Dec 19, 2019 Issued
Array ( [id] => 17107607 [patent_doc_number] => 11127835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Method for etching a three-dimensional dielectric layer [patent_app_type] => utility [patent_app_number] => 16/722390 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 14582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722390 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722390
Method for etching a three-dimensional dielectric layer Dec 19, 2019 Issued
Array ( [id] => 16081197 [patent_doc_number] => 20200194585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Power Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/713392 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713392
Ppower semiconductor device with anticorrosive edge termination structure Dec 12, 2019 Issued
Array ( [id] => 17439118 [patent_doc_number] => 11264459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Power semiconductor device [patent_app_type] => utility [patent_app_number] => 16/712120 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8660 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712120
Power semiconductor device Dec 11, 2019 Issued
Array ( [id] => 17723465 [patent_doc_number] => 20220216187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD OF TRANSFERRING MICRO LIGHT EMITTING DIODES AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/626554 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16626554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/626554
Method of transferring micro light emitting diodes and display panel Dec 9, 2019 Issued
Array ( [id] => 17032999 [patent_doc_number] => 11094819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Stacked vertical tunnel FET devices [patent_app_type] => utility [patent_app_number] => 16/705662 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8457 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705662
Stacked vertical tunnel FET devices Dec 5, 2019 Issued
Array ( [id] => 16001377 [patent_doc_number] => 20200176559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Method for Forming a Superjunction Transistor Device [patent_app_type] => utility [patent_app_number] => 16/697419 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697419
Method for forming a superjunction transistor device Nov 26, 2019 Issued
Array ( [id] => 16731423 [patent_doc_number] => 20210098571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SHALLOW TRENCH ISOLATION STRUCTURE AND SEMICONDUCTOR DEVICE WITH THE SAME [patent_app_type] => utility [patent_app_number] => 16/696765 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696765
Shallow trench isolation structure and semiconductor device with the same Nov 25, 2019 Issued
Array ( [id] => 16858568 [patent_doc_number] => 20210159313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => TRANSISTOR CELL FOR INTEGRATED CIRCUITS AND METHOD TO FORM SAME [patent_app_type] => utility [patent_app_number] => 16/693472 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693472
Transistor cell for integrated circuits and method to form same Nov 24, 2019 Issued
Array ( [id] => 16858591 [patent_doc_number] => 20210159336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR (FET) [patent_app_type] => utility [patent_app_number] => 16/691691 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691691
Vertical field effect transistor (FET) with source and drain structures Nov 21, 2019 Issued
Array ( [id] => 16973793 [patent_doc_number] => 11069775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS [patent_app_type] => utility [patent_app_number] => 16/690338 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5451 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690338
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS Nov 20, 2019 Issued
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