Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13435213 [patent_doc_number] => 20180269149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/979426 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979426
Memory device having capped embedded wires May 13, 2018 Issued
Array ( [id] => 13419951 [patent_doc_number] => 20180261518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR MODULE COMPRISING AN ENCAPSULATING COMPOUND THAT COVERS AT LEAST ONE SEMICONDUCTOR COMPONENT [patent_app_type] => utility [patent_app_number] => 15/974930 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974930
Semiconductor module comprising an encapsulating compound that covers at least one semiconductor component May 8, 2018 Issued
Array ( [id] => 14558325 [patent_doc_number] => 10347633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Spacer for trench epitaxial structures [patent_app_type] => utility [patent_app_number] => 15/972712 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972712
Spacer for trench epitaxial structures May 6, 2018 Issued
Array ( [id] => 14558323 [patent_doc_number] => 10347632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Forming spacer for trench epitaxial structures [patent_app_type] => utility [patent_app_number] => 15/972547 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3326 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972547
Forming spacer for trench epitaxial structures May 6, 2018 Issued
Array ( [id] => 16723988 [patent_doc_number] => 20210091135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => IMAGE SENSOR, IMAGE SENSOR MANUFACTURING METHOD, ELECTRONIC DEVICE, AND IMAGING MODULE [patent_app_type] => utility [patent_app_number] => 16/611973 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -51 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16611973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/611973
Optical filters and associated imaging devices Apr 30, 2018 Issued
Array ( [id] => 17166139 [patent_doc_number] => 11152251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Method for manufacturing semiconductor device having via formed by ion beam [patent_app_type] => utility [patent_app_number] => 15/965076 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 45 [patent_no_of_words] => 11645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/965076
Method for manufacturing semiconductor device having via formed by ion beam Apr 26, 2018 Issued
Array ( [id] => 16574937 [patent_doc_number] => 10896864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Power semiconductor chip module [patent_app_type] => utility [patent_app_number] => 15/964128 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5130 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964128 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964128
Power semiconductor chip module Apr 26, 2018 Issued
Array ( [id] => 15641195 [patent_doc_number] => 10593602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Semiconductor substrate crack mitigation systems and related methods [patent_app_type] => utility [patent_app_number] => 15/964484 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4546 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964484 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964484
Semiconductor substrate crack mitigation systems and related methods Apr 26, 2018 Issued
Array ( [id] => 15375731 [patent_doc_number] => 10529593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package [patent_app_type] => utility [patent_app_number] => 15/964092 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964092 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964092
Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package Apr 26, 2018 Issued
Array ( [id] => 16264667 [patent_doc_number] => 10756114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Semiconductor circuit with metal structure and manufacturing method [patent_app_type] => utility [patent_app_number] => 15/964216 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964216
Semiconductor circuit with metal structure and manufacturing method Apr 26, 2018 Issued
Array ( [id] => 14350367 [patent_doc_number] => 20190157156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING ISOLATION STRUCTURES WITH LINERS [patent_app_type] => utility [patent_app_number] => 15/964862 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964862
Methods of fabricating semiconductor devices having isolation structures with liners Apr 26, 2018 Issued
Array ( [id] => 16047961 [patent_doc_number] => 10685863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Wafer thinning systems and related methods [patent_app_type] => utility [patent_app_number] => 15/964464 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3740 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964464
Wafer thinning systems and related methods Apr 26, 2018 Issued
Array ( [id] => 15791521 [patent_doc_number] => 10629492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Gate structure having a dielectric gate and methods thereof [patent_app_type] => utility [patent_app_number] => 15/964177 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 6890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964177 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964177
Gate structure having a dielectric gate and methods thereof Apr 26, 2018 Issued
Array ( [id] => 14151635 [patent_doc_number] => 10256207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Clip-bonded semiconductor chip package using metal bumps and method for manufacturing the package [patent_app_type] => utility [patent_app_number] => 15/958581 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4829 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958581 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/958581
Clip-bonded semiconductor chip package using metal bumps and method for manufacturing the package Apr 19, 2018 Issued
Array ( [id] => 18131430 [patent_doc_number] => 11557647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/048174 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 8819 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17048174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/048174
Semiconductor device and manufacturing method thereof Apr 18, 2018 Issued
Array ( [id] => 13976777 [patent_doc_number] => 10217756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Method for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/951070 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951070
Method for fabricating semiconductor device Apr 10, 2018 Issued
Array ( [id] => 15580609 [patent_doc_number] => 10580697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Workpiece dividing method [patent_app_type] => utility [patent_app_number] => 15/946293 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946293
Workpiece dividing method Apr 4, 2018 Issued
Array ( [id] => 13785985 [patent_doc_number] => 20190006531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => CISCSP Package and Related Methods [patent_app_type] => utility [patent_app_number] => 15/939582 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939582
CISCSP Package and Related Methods Mar 28, 2018 Abandoned
Array ( [id] => 16372374 [patent_doc_number] => 10804140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Interconnect formation and structure [patent_app_type] => utility [patent_app_number] => 15/939572 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8706 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939572
Interconnect formation and structure Mar 28, 2018 Issued
Array ( [id] => 14587787 [patent_doc_number] => 20190221502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Down Bond in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 15/939586 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939586
Down Bond in Semiconductor Devices Mar 28, 2018 Abandoned
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