
Mohammad M. Hoque
Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2817, 2823 |
| Total Applications | 867 |
| Issued Applications | 667 |
| Pending Applications | 103 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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