
Mohammad M. Hoque
Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2817, 2823 |
| Total Applications | 867 |
| Issued Applications | 667 |
| Pending Applications | 103 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15890911
[patent_doc_number] => 10651817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Bulk acoustic wave resonator on a stress isolated platform
[patent_app_type] => utility
[patent_app_number] => 15/857906
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 3947
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857906
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/857906 | Bulk acoustic wave resonator on a stress isolated platform | Dec 28, 2017 | Issued |
Array
(
[id] => 14542509
[patent_doc_number] => 20190206876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => Construction Of Integrated Circuitry And A DRAM Construction
[patent_app_type] => utility
[patent_app_number] => 15/858263
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4490
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858263
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/858263 | Construction of integrated circuitry and a DRAM construction | Dec 28, 2017 | Issued |
Array
(
[id] => 13606465
[patent_doc_number] => 20180354781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/855097
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5219
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855097
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/855097 | BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | Dec 26, 2017 | Abandoned |
Array
(
[id] => 15776339
[patent_doc_number] => 20200119187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => MOSFET, METHOD OF MANUFACTURING MOSFET, AND POWER CONVERSION CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/603700
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603700
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/603700 | MOSFET, having a semiconductor base substrate with a super junction structure, method of manufacturing the MOSFET, and power conversion circuit having the MOSFET | Dec 26, 2017 | Issued |
Array
(
[id] => 16410089
[patent_doc_number] => 10818653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Control circuit and operating circuit utilizing the same
[patent_app_type] => utility
[patent_app_number] => 15/839197
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2709
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839197
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839197 | Control circuit and operating circuit utilizing the same | Dec 11, 2017 | Issued |
Array
(
[id] => 15185031
[patent_doc_number] => 20190363107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => DISPLAY DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/477681
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11108
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477681
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/477681 | Display device and electronic device with microlens array and light emitting element substrates bonded by adhesive layer | Dec 11, 2017 | Issued |
Array
(
[id] => 12849457
[patent_doc_number] => 20180174992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => SEMICONDUCTOR DEVICE WITH COPPER MIGRATION STOPPING OF A REDISTRIBUTION LAYER
[patent_app_type] => utility
[patent_app_number] => 15/839818
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4583
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839818
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839818 | SEMICONDUCTOR DEVICE WITH COPPER MIGRATION STOPPING OF A REDISTRIBUTION LAYER | Dec 11, 2017 | Abandoned |
Array
(
[id] => 14446541
[patent_doc_number] => 20190181144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => DEVICE STRUCTURE FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONTACTS
[patent_app_type] => utility
[patent_app_number] => 15/839260
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4878
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839260
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839260 | Device structure for forming semiconductor device having angled contacts | Dec 11, 2017 | Issued |
Array
(
[id] => 15733369
[patent_doc_number] => 10615119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-07
[patent_title] => Back end of line electrical fuse structure and method of fabrication
[patent_app_type] => utility
[patent_app_number] => 15/839505
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 10491
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 345
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839505
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839505 | Back end of line electrical fuse structure and method of fabrication | Dec 11, 2017 | Issued |
Array
(
[id] => 12668812
[patent_doc_number] => 20180114770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => Substrateless Integrated Circuit Packages and Methods of Forming Same
[patent_app_type] => utility
[patent_app_number] => 15/837704
[patent_app_country] => US
[patent_app_date] => 2017-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5482
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837704
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/837704 | Substrateless integrated circuit packages and methods of forming same | Dec 10, 2017 | Issued |
Array
(
[id] => 15565157
[patent_doc_number] => 20200066990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => PREPARATION PROCESS FOR AN ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/466487
[patent_app_country] => US
[patent_app_date] => 2017-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20552
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16466487
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/466487 | Process for making electronic device | Dec 3, 2017 | Issued |
Array
(
[id] => 14125733
[patent_doc_number] => 10249732
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-02
[patent_title] => Manufacturing method of semiconductor device to uniformly form thickness of gate insulating layer
[patent_app_type] => utility
[patent_app_number] => 15/823856
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3725
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823856
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/823856 | Manufacturing method of semiconductor device to uniformly form thickness of gate insulating layer | Nov 27, 2017 | Issued |
Array
(
[id] => 14381721
[patent_doc_number] => 20190164773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => METHOD OF FORMING FIELD EFFECT TRANSISTOR (FET) CIRCUITS, AND FORMING INTEGRATED CIRCUIT (IC) CHIPS WITH THE FET CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 15/824175
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2257
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824175
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/824175 | Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits | Nov 27, 2017 | Issued |
Array
(
[id] => 12236027
[patent_doc_number] => 20180068890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'METHOD OF ENABLING SEAMLESS COBALT GAP-FILL'
[patent_app_type] => utility
[patent_app_number] => 15/811647
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13544
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811647
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811647 | Method of enabling seamless cobalt gap-fill | Nov 12, 2017 | Issued |
Array
(
[id] => 17516959
[patent_doc_number] => 11296120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Shift register and display device and driving method thereof
[patent_app_type] => utility
[patent_app_number] => 15/806418
[patent_app_country] => US
[patent_app_date] => 2017-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 53
[patent_no_of_words] => 25052
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806418
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/806418 | Shift register and display device and driving method thereof | Nov 7, 2017 | Issued |
Array
(
[id] => 12208424
[patent_doc_number] => 20180053650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-22
[patent_title] => 'LOW EXTERNAL RESISTANCE CHANNELS IN III-V SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/799579
[patent_app_country] => US
[patent_app_date] => 2017-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4659
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799579
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/799579 | Low external resistance channels in III-V semiconductor devices | Oct 30, 2017 | Issued |
Array
(
[id] => 14238189
[patent_doc_number] => 20190131267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-02
[patent_title] => OPTICAL SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/796091
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8349
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796091
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/796091 | Optical semiconductor package and method for manufacturing the same | Oct 26, 2017 | Issued |
Array
(
[id] => 14191481
[patent_doc_number] => 20190115446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING N-TYPE CONDUCTIVE CHANNEL IN DIAMOND USING HETEROJUNCTION
[patent_app_type] => utility
[patent_app_number] => 15/796265
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796265
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/796265 | Semiconductor device and method for forming n-type conductive channel in diamond using heterojunction | Oct 26, 2017 | Issued |
Array
(
[id] => 13528739
[patent_doc_number] => 20180315912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => LIGHT EMITTING DEVICE PACKAGE
[patent_app_type] => utility
[patent_app_number] => 15/796190
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9177
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796190
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/796190 | Light emitting device package including a lead frame | Oct 26, 2017 | Issued |
Array
(
[id] => 15286671
[patent_doc_number] => 10516005
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-24
[patent_title] => Display substrate of electronic device and method for manufacturing same
[patent_app_type] => utility
[patent_app_number] => 15/792926
[patent_app_country] => US
[patent_app_date] => 2017-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4202
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792926
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/792926 | Display substrate of electronic device and method for manufacturing same | Oct 24, 2017 | Issued |