
Mohammad M. Hoque
Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2817, 2823 |
| Total Applications | 867 |
| Issued Applications | 667 |
| Pending Applications | 103 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13349957
[patent_doc_number] => 20180226518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => METHOD OF MANUFACTURING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT
[patent_app_type] => utility
[patent_app_number] => 15/749656
[patent_app_country] => US
[patent_app_date] => 2016-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6849
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749656
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/749656 | METHOD OF MANUFACTURING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT | Aug 1, 2016 | Abandoned |
Array
(
[id] => 13350003
[patent_doc_number] => 20180226541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => LIGHT EMITTING ELEMENT
[patent_app_type] => utility
[patent_app_number] => 15/749730
[patent_app_country] => US
[patent_app_date] => 2016-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749730
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/749730 | Light emitting element having excellent contact between semiconductor layer and electrode | Jul 28, 2016 | Issued |
Array
(
[id] => 11132274
[patent_doc_number] => 20160329249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 15/211256
[patent_app_country] => US
[patent_app_date] => 2016-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6311
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211256
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/211256 | Isolation components for transistors formed on fin features of semiconductor substrates | Jul 14, 2016 | Issued |
Array
(
[id] => 11125412
[patent_doc_number] => 20160322386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'Method of Forming a Semiconductor Substrate With Buried Cavities and Dielectric Support Structures'
[patent_app_type] => utility
[patent_app_number] => 15/209206
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7212
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209206
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209206 | Semiconductor device with buried cavities and dielectric support structures | Jul 12, 2016 | Issued |
Array
(
[id] => 11087657
[patent_doc_number] => 20160284625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-29
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE WITH STATOR SET FORMED BY CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 15/178632
[patent_app_country] => US
[patent_app_date] => 2016-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4883
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178632
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/178632 | Method for fabricating semiconductor package with stator set formed by circuits | Jun 9, 2016 | Issued |
Array
(
[id] => 14526219
[patent_doc_number] => 10340380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-02
[patent_title] => Three-dimensional transistor with improved channel mobility
[patent_app_type] => utility
[patent_app_number] => 15/161399
[patent_app_country] => US
[patent_app_date] => 2016-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 26
[patent_no_of_words] => 6595
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161399
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161399 | Three-dimensional transistor with improved channel mobility | May 22, 2016 | Issued |
Array
(
[id] => 11057388
[patent_doc_number] => 20160254350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-01
[patent_title] => 'METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 15/152249
[patent_app_country] => US
[patent_app_date] => 2016-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7499
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15152249
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/152249 | Method of formation of germanium nanowires on bulk substrates | May 10, 2016 | Issued |
Array
(
[id] => 12089036
[patent_doc_number] => 09842769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-12
[patent_title] => 'Method of enabling seamless cobalt gap-fill'
[patent_app_type] => utility
[patent_app_number] => 15/145578
[patent_app_country] => US
[patent_app_date] => 2016-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 13524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145578
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/145578 | Method of enabling seamless cobalt gap-fill | May 2, 2016 | Issued |
Array
(
[id] => 11021244
[patent_doc_number] => 20160218198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-28
[patent_title] => 'ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET'
[patent_app_type] => utility
[patent_app_number] => 15/092039
[patent_app_country] => US
[patent_app_date] => 2016-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8184
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092039
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/092039 | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET | Apr 5, 2016 | Issued |
Array
(
[id] => 11010804
[patent_doc_number] => 20160207757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'MEMS DEVICE AND CORRESPONDING MICROMECHANICAL STRUCTURE WITH INTEGRATED COMPENSATION OF THERMO-MECHANICAL STRESS'
[patent_app_type] => utility
[patent_app_number] => 15/085901
[patent_app_country] => US
[patent_app_date] => 2016-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6580
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085901
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/085901 | MEMS device and corresponding micromechanical structure with integrated compensation of thermo-mechanical stress | Mar 29, 2016 | Issued |
Array
(
[id] => 18205610
[patent_doc_number] => 11588017
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Nanowire for transistor integration
[patent_app_type] => utility
[patent_app_number] => 16/085237
[patent_app_country] => US
[patent_app_date] => 2016-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6756
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16085237
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/085237 | Nanowire for transistor integration | Mar 29, 2016 | Issued |
Array
(
[id] => 13848389
[patent_doc_number] => 20190027679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => APPROACHES FOR STRAIN ENGINEERING OF PERPENDICULAR MAGNETIC TUNNEL JUNCTIONS (PMTJS) AND THE RESULTING STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/070415
[patent_app_country] => US
[patent_app_date] => 2016-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9001
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070415
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/070415 | Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures | Mar 29, 2016 | Issued |
Array
(
[id] => 11007297
[patent_doc_number] => 20160204248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-14
[patent_title] => 'SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/075078
[patent_app_country] => US
[patent_app_date] => 2016-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 13303
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075078
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/075078 | Semiconductor device with vertical gate and method of manufacturing the same | Mar 17, 2016 | Issued |
Array
(
[id] => 12019818
[patent_doc_number] => 09812530
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'High germanium content silicon germanium fins'
[patent_app_type] => utility
[patent_app_number] => 15/068601
[patent_app_country] => US
[patent_app_date] => 2016-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5438
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068601
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/068601 | High germanium content silicon germanium fins | Mar 12, 2016 | Issued |
Array
(
[id] => 11952298
[patent_doc_number] => 20170256449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-07
[patent_title] => 'METHODS OF FORMING CONDUCTIVE STRUCTURES WITH DIFFERENT MATERIAL COMPOSITIONS IN A METALLIZATION LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/062328
[patent_app_country] => US
[patent_app_date] => 2016-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7340
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062328
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/062328 | METHODS OF FORMING CONDUCTIVE STRUCTURES WITH DIFFERENT MATERIAL COMPOSITIONS IN A METALLIZATION LAYER | Mar 6, 2016 | Abandoned |
Array
(
[id] => 11918368
[patent_doc_number] => 09786559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-10
[patent_title] => 'Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (TSVs)'
[patent_app_type] => utility
[patent_app_number] => 15/044976
[patent_app_country] => US
[patent_app_date] => 2016-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 8474
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044976
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/044976 | Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (TSVs) | Feb 15, 2016 | Issued |
Array
(
[id] => 10817680
[patent_doc_number] => 20160163842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'FORMATION OF CMOS DEVICE USING CARBON NANOTUBES'
[patent_app_type] => utility
[patent_app_number] => 15/016716
[patent_app_country] => US
[patent_app_date] => 2016-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5210
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016716
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/016716 | CMOS device having carbon nanotubes | Feb 4, 2016 | Issued |
Array
(
[id] => 11824951
[patent_doc_number] => 20170213888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-27
[patent_title] => 'SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS'
[patent_app_type] => utility
[patent_app_number] => 15/007920
[patent_app_country] => US
[patent_app_date] => 2016-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5592
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007920
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/007920 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Jan 26, 2016 | Issued |
Array
(
[id] => 11821676
[patent_doc_number] => 20170210613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-27
[patent_title] => 'NANO-ELECTROMECHANICAL SYSTEM (NEMS) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/007852
[patent_app_country] => US
[patent_app_date] => 2016-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 7834
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007852
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/007852 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Jan 26, 2016 | Issued |
Array
(
[id] => 11021303
[patent_doc_number] => 20160218257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-28
[patent_title] => 'PRINTED LED LIGHT SHEETS WITH REDUCED VISIBILITY OF PHOSPHOR LAYER IN OFF STATE'
[patent_app_type] => utility
[patent_app_number] => 15/008383
[patent_app_country] => US
[patent_app_date] => 2016-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12609
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008383
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/008383 | PRINTED LED LIGHT SHEETS WITH REDUCED VISIBILITY OF PHOSPHOR LAYER IN OFF STATE | Jan 26, 2016 | Abandoned |