
Mohammad M. Hoque
Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2817, 2823 |
| Total Applications | 867 |
| Issued Applications | 667 |
| Pending Applications | 103 |
| Abandoned Applications | 114 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10631546
[patent_doc_number] => 09349702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-24
[patent_title] => 'Chip bonding method and driving chip of display'
[patent_app_type] => utility
[patent_app_number] => 14/557776
[patent_app_country] => US
[patent_app_date] => 2014-12-02
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Array
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[patent_issue_date] => 2017-05-09
[patent_title] => 'Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/557907 | Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films | Dec 1, 2014 | Issued |
Array
(
[id] => 10709950
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[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'SEMICONDUCTOR DEVICE WITH INSPECTABLE SOLDER JOINTS'
[patent_app_type] => utility
[patent_app_number] => 14/556225
[patent_app_country] => US
[patent_app_date] => 2014-11-30
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Array
(
[id] => 11071356
[patent_doc_number] => 20160268320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'Array Substrate, Manufacturing Method Thereof and Display Apparatus'
[patent_app_type] => utility
[patent_app_number] => 14/772677
[patent_app_country] => US
[patent_app_date] => 2014-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/772677 | Array substrate manufactured by reduced times of patterning processes manufacturing method thereof and display apparatus | Nov 20, 2014 | Issued |
Array
(
[id] => 10747541
[patent_doc_number] => 20160093691
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[patent_kind] => A1
[patent_issue_date] => 2016-03-31
[patent_title] => 'SEMICONDUCTOR DEVICE, ELECTRIC EQUIPMENT, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTED STRUCTURE BODY'
[patent_app_type] => utility
[patent_app_number] => 14/890659
[patent_app_country] => US
[patent_app_date] => 2014-11-18
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 12498867
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[patent_title] => Semiconductor device, display device, and electronic device
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Array
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[id] => 10525703
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[patent_title] => 'Semiconductor device having a buried gate'
[patent_app_type] => utility
[patent_app_number] => 14/531778
[patent_app_country] => US
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Array
(
[id] => 9861841
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[patent_issue_date] => 2015-02-12
[patent_title] => '3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/522649
[patent_app_country] => US
[patent_app_date] => 2014-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/522649 | 3D transistor channel mobility enhancement | Oct 23, 2014 | Issued |
Array
(
[id] => 10772250
[patent_doc_number] => 20160118406
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[patent_issue_date] => 2016-04-28
[patent_title] => 'Semiconductor Structure with Active Device and Damaged Region'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/521327 | Semiconductor structure with active device and damaged region | Oct 21, 2014 | Issued |
Array
(
[id] => 9799122
[patent_doc_number] => 20150011066
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[patent_kind] => A1
[patent_issue_date] => 2015-01-08
[patent_title] => 'SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/497615
[patent_app_country] => US
[patent_app_date] => 2014-09-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/497615 | Semiconductor device with vertical gate and method of manufacturing the same | Sep 25, 2014 | Issued |
Array
(
[id] => 11967348
[patent_doc_number] => 20170271501
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[patent_issue_date] => 2017-09-21
[patent_title] => 'SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION'
[patent_app_type] => utility
[patent_app_number] => 15/505558
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/505558 | Scaled TFET transistor formed using nanowire with surface termination | Sep 23, 2014 | Issued |
Array
(
[id] => 9789681
[patent_doc_number] => 20150001625
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[patent_kind] => A1
[patent_issue_date] => 2015-01-01
[patent_title] => 'STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS'
[patent_app_type] => utility
[patent_app_number] => 14/490711
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Array
(
[id] => 9792602
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[patent_kind] => A1
[patent_issue_date] => 2015-01-01
[patent_title] => 'METHOD FOR FABRICATING PHOTO SPACER'
[patent_app_type] => utility
[patent_app_number] => 14/487102
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Array
(
[id] => 10725612
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Array
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Array
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Array
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Array
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