Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10631546 [patent_doc_number] => 09349702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Chip bonding method and driving chip of display' [patent_app_type] => utility [patent_app_number] => 14/557776 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4845 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557776 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557776
Chip bonding method and driving chip of display Dec 1, 2014 Issued
Array ( [id] => 11597133 [patent_doc_number] => 09644287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films' [patent_app_type] => utility [patent_app_number] => 14/557907 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10813 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557907 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557907
Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films Dec 1, 2014 Issued
Array ( [id] => 10709950 [patent_doc_number] => 20160056097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'SEMICONDUCTOR DEVICE WITH INSPECTABLE SOLDER JOINTS' [patent_app_type] => utility [patent_app_number] => 14/556225 [patent_app_country] => US [patent_app_date] => 2014-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556225
SEMICONDUCTOR DEVICE WITH INSPECTABLE SOLDER JOINTS Nov 29, 2014 Abandoned
Array ( [id] => 11071356 [patent_doc_number] => 20160268320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'Array Substrate, Manufacturing Method Thereof and Display Apparatus' [patent_app_type] => utility [patent_app_number] => 14/772677 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13375 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14772677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/772677
Array substrate manufactured by reduced times of patterning processes manufacturing method thereof and display apparatus Nov 20, 2014 Issued
Array ( [id] => 10747541 [patent_doc_number] => 20160093691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SEMICONDUCTOR DEVICE, ELECTRIC EQUIPMENT, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTED STRUCTURE BODY' [patent_app_type] => utility [patent_app_number] => 14/890659 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 32349 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14890659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/890659
Semiconductor device having a polarization super junction field effect transistor, electric equipment, bidirectional field effect transistor, and mounted structure body having the same Nov 17, 2014 Issued
Array ( [id] => 12498867 [patent_doc_number] => 09997584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Semiconductor device, display device, and electronic device [patent_app_type] => utility [patent_app_number] => 14/541255 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 72 [patent_no_of_words] => 32474 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541255
Semiconductor device, display device, and electronic device Nov 13, 2014 Issued
Array ( [id] => 10525703 [patent_doc_number] => 09252223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Semiconductor device having a buried gate' [patent_app_type] => utility [patent_app_number] => 14/531778 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4081 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531778
Semiconductor device having a buried gate Nov 2, 2014 Issued
Array ( [id] => 9861841 [patent_doc_number] => 20150041858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => '3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 14/522649 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522649
3D transistor channel mobility enhancement Oct 23, 2014 Issued
Array ( [id] => 10772250 [patent_doc_number] => 20160118406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'Semiconductor Structure with Active Device and Damaged Region' [patent_app_type] => utility [patent_app_number] => 14/521327 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521327 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521327
Semiconductor structure with active device and damaged region Oct 21, 2014 Issued
Array ( [id] => 9799122 [patent_doc_number] => 20150011066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/497615 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/497615
Semiconductor device with vertical gate and method of manufacturing the same Sep 25, 2014 Issued
Array ( [id] => 11967348 [patent_doc_number] => 20170271501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION' [patent_app_type] => utility [patent_app_number] => 15/505558 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6514 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15505558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/505558
Scaled TFET transistor formed using nanowire with surface termination Sep 23, 2014 Issued
Array ( [id] => 9789681 [patent_doc_number] => 20150001625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS' [patent_app_type] => utility [patent_app_number] => 14/490711 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5349 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/490711
STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS Sep 18, 2014 Abandoned
Array ( [id] => 9792602 [patent_doc_number] => 20150004546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'METHOD FOR FABRICATING PHOTO SPACER' [patent_app_type] => utility [patent_app_number] => 14/487102 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4558 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487102
METHOD FOR FABRICATING PHOTO SPACER Sep 15, 2014 Abandoned
Array ( [id] => 10725612 [patent_doc_number] => 20160071759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'Method of Forming a Semiconductor Substrate With Buried Cavities and Dielectric Support Structures' [patent_app_type] => utility [patent_app_number] => 14/479518 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479518 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479518
Method of forming a semiconductor substrate with buried cavities and dielectric support structures Sep 7, 2014 Issued
Array ( [id] => 10373761 [patent_doc_number] => 20150258767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SUBSTRATE PEELING APPARATUS AND METHOD OF FABRICATING DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/479715 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479715 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479715
Substrate peeling apparatus and method of fabricating device using the same Sep 7, 2014 Issued
Array ( [id] => 10725820 [patent_doc_number] => 20160071968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'LOW EXTERNAL RESISTANCE CHANNELS IN III-V SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/479504 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479504
Low external resistance channels in III-V semiconductor devices Sep 7, 2014 Issued
Array ( [id] => 10383495 [patent_doc_number] => 20150268502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/479585 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479585
Liquid crystal display and method for fabricating the same Sep 7, 2014 Issued
Array ( [id] => 10377826 [patent_doc_number] => 20150262832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/479590 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 8088 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479590
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Sep 7, 2014 Abandoned
Array ( [id] => 10189544 [patent_doc_number] => 09218972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-22 [patent_title] => 'Pattern forming method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/479570 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2049 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479570
Pattern forming method for manufacturing semiconductor device Sep 7, 2014 Issued
Array ( [id] => 10604271 [patent_doc_number] => 09324843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'High germanium content silicon germanium fins' [patent_app_type] => utility [patent_app_number] => 14/479252 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5380 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479252 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479252
High germanium content silicon germanium fins Sep 4, 2014 Issued
Menu