Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9626410 [patent_doc_number] => 08796090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Semiconductor device with vertical channel transistor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/716931 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 7884 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716931 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716931
Semiconductor device with vertical channel transistor and method for fabricating the same Dec 16, 2012 Issued
Array ( [id] => 10073533 [patent_doc_number] => 09111897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/716859 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 8227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716859
Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices Dec 16, 2012 Issued
Array ( [id] => 9306662 [patent_doc_number] => 20140045336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/715500 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715500
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Dec 13, 2012 Abandoned
Array ( [id] => 8916436 [patent_doc_number] => 20130178061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'METHOD OF MANUFACTURING POROUS FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/715280 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4888 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715280
METHOD OF MANUFACTURING POROUS FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Dec 13, 2012 Abandoned
Array ( [id] => 8818388 [patent_doc_number] => 20130119432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/712812 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16430 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13712812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/712812
Semiconductor device with low-lifetime region Dec 11, 2012 Issued
Array ( [id] => 8764926 [patent_doc_number] => 20130092963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/691286 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 33157 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691286
Semiconductor device, display device, and electronic device Nov 29, 2012 Issued
Array ( [id] => 8777378 [patent_doc_number] => 20130099353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'ESD PROTECTION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/689983 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689983
ESD protection device Nov 29, 2012 Issued
Array ( [id] => 8753504 [patent_doc_number] => 20130087808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SIC BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN EMITTER' [patent_app_type] => utility [patent_app_number] => 13/688067 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16451 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13688067 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/688067
SiC bipolar junction transistor with overgrown emitter Nov 27, 2012 Issued
Array ( [id] => 10876194 [patent_doc_number] => 08900979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films' [patent_app_type] => utility [patent_app_number] => 13/682240 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10784 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/682240
Pretreatment method for reduction and/or elimination of basal plane dislocations close to epilayer/substrate interface in growth of SiC epitaxial films Nov 19, 2012 Issued
Array ( [id] => 11535652 [patent_doc_number] => 09610044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Variable capacitor circuit and method' [patent_app_type] => utility [patent_app_number] => 13/671164 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2042 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671164
Variable capacitor circuit and method Nov 6, 2012 Issued
Array ( [id] => 9280904 [patent_doc_number] => 20140030872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'NANO-STRUCTURE MANUFACTURING METHOD USING SACRIFICIAL ETCHING MASK' [patent_app_type] => utility [patent_app_number] => 13/668526 [patent_app_country] => US [patent_app_date] => 2012-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13668526 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/668526
Nano-structure manufacturing method using sacrificial etching mask Nov 4, 2012 Issued
Array ( [id] => 12215022 [patent_doc_number] => 09911838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'IGBT die structure with auxiliary P well terminal' [patent_app_type] => utility [patent_app_number] => 13/662384 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 10197 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662384
IGBT die structure with auxiliary P well terminal Oct 25, 2012 Issued
Array ( [id] => 9716645 [patent_doc_number] => 20140252343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'THIN-FILM TRANSISTOR ACTIVE DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 13/806821 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13806821 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/806821
THIN-FILM TRANSISTOR ACTIVE DEVICE AND METHOD FOR MANUFACTURING SAME Oct 23, 2012 Abandoned
Array ( [id] => 9432861 [patent_doc_number] => 20140110767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'BULK FINFET WELL CONTACTS WITH FIN PATTERN UNIFORMITY' [patent_app_type] => utility [patent_app_number] => 13/659292 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659292
Bulk finFET well contacts with fin pattern uniformity Oct 23, 2012 Issued
Array ( [id] => 8863264 [patent_doc_number] => 20130146967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Trench-Gate Resurf Semiconductor Device and Manufacturing Method' [patent_app_type] => utility [patent_app_number] => 13/659678 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3470 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659678 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659678
Trench-gate RESURF semiconductor device and manufacturing method Oct 23, 2012 Issued
Array ( [id] => 9432859 [patent_doc_number] => 20140110765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'FIELD EFFECT TRANSISTOR HAVING PHASE TRANSITION MATERIAL INCORPORATED INTO ONE OR MORE COMPONENTS FOR REDUCED LEAKAGE CURRENT' [patent_app_type] => utility [patent_app_number] => 13/656819 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11255 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656819
Field effect transistor having phase transition material incorporated into one or more components for reduced leakage current Oct 21, 2012 Issued
Array ( [id] => 8779275 [patent_doc_number] => 20130101250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'Molded Glass Lid For Wafer Level Packaging Of Opto-Electronic Assemblies' [patent_app_type] => utility [patent_app_number] => 13/656528 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656528
Molded glass lid for wafer level packaging of opto-electronic assemblies Oct 18, 2012 Issued
Array ( [id] => 9432871 [patent_doc_number] => 20140110777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/654432 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3590 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654432 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654432
TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF Oct 17, 2012 Abandoned
Array ( [id] => 8657052 [patent_doc_number] => 20130037881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/653512 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13304 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653512
SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME Oct 16, 2012 Abandoned
Array ( [id] => 10073661 [patent_doc_number] => 09112026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Semiconductor devices and method of making the same' [patent_app_type] => utility [patent_app_number] => 13/654143 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7171 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654143
Semiconductor devices and method of making the same Oct 16, 2012 Issued
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