Search

Mohammad M. Hoque

Examiner (ID: 652, Phone: (571)272-6266 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2823
Total Applications
867
Issued Applications
667
Pending Applications
103
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20792738 [patent_doc_number] => 12666670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Semiconductor device with source region having multiple portions with different impulity concentrations and method for the same [patent_app_type] => utility [patent_app_number] => 18/179059 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 4983 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179059
Semiconductor device with source region having multiple portions with different impulity concentrations and method for the same Mar 5, 2023 Issued
Array ( [id] => 18514756 [patent_doc_number] => 20230231019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => GaN/DIAMOND WAFERS [patent_app_type] => utility [patent_app_number] => 18/176427 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176427
Method of forming vias in a GaN/diamond wafer Feb 27, 2023 Issued
Array ( [id] => 19055052 [patent_doc_number] => 20240097021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/113445 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113445
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Feb 22, 2023 Pending
Array ( [id] => 18600321 [patent_doc_number] => 20230275122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/170767 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170767
SILICON CARBIDE SEMICONDUCTOR DEVICE Feb 16, 2023 Issued
Array ( [id] => 18586156 [patent_doc_number] => 20230268421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD FOR AUTO-ALIGNED MANUFACTURING OF A TRENCH-GATE MOS TRANSISTOR, AND SHIELDED-GATE MOS TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/168509 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168509
METHOD FOR AUTO-ALIGNED MANUFACTURING OF A TRENCH-GATE MOS TRANSISTOR, AND SHIELDED-GATE MOS TRANSISTOR Feb 12, 2023 Pending
Array ( [id] => 19055003 [patent_doc_number] => 20240096972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/168243 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168243
Semiconductor device having a structure in which a field plate electrode and a gate electrode are buried in different trenches Feb 12, 2023 Issued
Array ( [id] => 21014561 [patent_doc_number] => 12751059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-29 [patent_title] => Semiconductor device with metal silicide layer and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/166230 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6728 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166230
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Feb 7, 2023 Pending
Array ( [id] => 19364356 [patent_doc_number] => 20240266390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 18/107377 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107377
Semiconductor switching device Feb 7, 2023 Issued
Array ( [id] => 19364357 [patent_doc_number] => 20240266391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/164319 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164319
Semiconductor device and method for forming the same with doping regions having different conductivity types Feb 2, 2023 Issued
Array ( [id] => 20405596 [patent_doc_number] => 12495586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Superjunction semiconductor device and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 18/146629 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 1208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146629
Superjunction semiconductor device and method of manufacturing same Dec 26, 2022 Issued
Array ( [id] => 18336830 [patent_doc_number] => 20230128779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => FILLING OPENINGS BY COMBINING NON-FLOWABLE AND FLOWABLE PROCESSES [patent_app_type] => utility [patent_app_number] => 18/088467 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088467 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088467
Filling openings by combining non-flowable and flowable processes Dec 22, 2022 Issued
Array ( [id] => 18323842 [patent_doc_number] => 20230121970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/080933 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080933
Semiconductor device having thermally conductive electrodes Dec 13, 2022 Issued
Array ( [id] => 20675303 [patent_doc_number] => 12615836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Trench field effect transistor having improved electrical performance [patent_app_type] => utility [patent_app_number] => 18/081391 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 4565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081391
Trench field effect transistor having improved electrical performance Dec 13, 2022 Issued
Array ( [id] => 18296394 [patent_doc_number] => 20230106080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => UP-DIFFUSION SUPPRESSION IN A POWER MOSFET [patent_app_type] => utility [patent_app_number] => 18/063086 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063086
Up-diffusion suppression in a power MOSFET Dec 7, 2022 Issued
Array ( [id] => 18293618 [patent_doc_number] => 20230103304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/077731 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077731
High voltage edge termination structure for power semiconductor devices and manufacturing method thereof Dec 7, 2022 Issued
Array ( [id] => 18298982 [patent_doc_number] => 20230108668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/077670 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077670
High voltage edge termination structure for power semiconductor devices and manufacturing method thereof Dec 7, 2022 Issued
Array ( [id] => 18295092 [patent_doc_number] => 20230104778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/077790 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077790
High voltage edge termination structure for power semiconductor devices Dec 7, 2022 Issued
Array ( [id] => 18298663 [patent_doc_number] => 20230108349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => VOLTAGE-SUSTAINING LAYER FOR SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 18/063572 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063572
VOLTAGE-SUSTAINING LAYER FOR SEMICONDUCTORS Dec 7, 2022 Issued
Array ( [id] => 18600331 [patent_doc_number] => 20230275132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/062827 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062827
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Dec 6, 2022 Pending
Array ( [id] => 19494379 [patent_doc_number] => 12113103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Charge-balance power device, and process for manufacturing the charge-balance power device [patent_app_type] => utility [patent_app_number] => 18/062524 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8294 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062524
Charge-balance power device, and process for manufacturing the charge-balance power device Dec 5, 2022 Issued
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