Search

Mohammed A. Bashar

Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
746
Issued Applications
652
Pending Applications
90
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18704491 [patent_doc_number] => 11791007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Leakage detection circuit, nonvolatile memory device including leakage detection circuit, and memory system including nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/576480 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576480
Leakage detection circuit, nonvolatile memory device including leakage detection circuit, and memory system including nonvolatile memory device Jan 13, 2022 Issued
Array ( [id] => 18286113 [patent_doc_number] => 20230101585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Method of Determining Defective Die Containing Non-volatile Memory Cells [patent_app_type] => utility [patent_app_number] => 17/576754 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576754
Method of determining defective die containing non-volatile memory cells Jan 13, 2022 Issued
Array ( [id] => 18154717 [patent_doc_number] => 11567695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Buffer circuit with data bit inversion [patent_app_type] => utility [patent_app_number] => 17/575524 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575524
Buffer circuit with data bit inversion Jan 12, 2022 Issued
Array ( [id] => 20317983 [patent_doc_number] => 12456538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 18/261631 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3635 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/261631
Semiconductor storage device Jan 11, 2022 Issued
Array ( [id] => 18950790 [patent_doc_number] => 11894093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Stacked DRAM device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/568649 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568649
Stacked DRAM device and method of manufacture Jan 3, 2022 Issued
Array ( [id] => 17550176 [patent_doc_number] => 20220121518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/562505 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562505
Semiconductor memory devices, memory systems including the same and methods of operating memory systems Dec 26, 2021 Issued
Array ( [id] => 18781996 [patent_doc_number] => 11823761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Pre-read in opposite polarity to evaluate read margin [patent_app_type] => utility [patent_app_number] => 17/561008 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 13608 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561008
Pre-read in opposite polarity to evaluate read margin Dec 22, 2021 Issued
Array ( [id] => 18226171 [patent_doc_number] => 20230065165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WRITE-ASSIST FOR SEQUENTIAL SRAM [patent_app_type] => utility [patent_app_number] => 17/554838 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554838
WRITE-ASSIST FOR SEQUENTIAL SRAM Dec 16, 2021 Abandoned
Array ( [id] => 18528546 [patent_doc_number] => 11715544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => System and method for low power memory test [patent_app_type] => utility [patent_app_number] => 17/538942 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538942
System and method for low power memory test Nov 29, 2021 Issued
Array ( [id] => 17963414 [patent_doc_number] => 20220343995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SYSTEM AND METHOD FOR PARALLEL MEMORY TEST [patent_app_type] => utility [patent_app_number] => 17/538982 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538982
System and method for parallel memory test Nov 29, 2021 Issued
Array ( [id] => 17462413 [patent_doc_number] => 20220075718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Keeping Zones Open With Intermediate Padding [patent_app_type] => utility [patent_app_number] => 17/455887 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455887
Keeping zones open with intermediate padding Nov 18, 2021 Issued
Array ( [id] => 19252520 [patent_doc_number] => 20240203517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Logical Memory Repair with a Shared Physical Memory [patent_app_type] => utility [patent_app_number] => 18/556858 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18556858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/556858
Logical Memory Repair with a Shared Physical Memory Nov 16, 2021 Issued
Array ( [id] => 17643805 [patent_doc_number] => 20220171543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => MEMORY WITH FUSE PINS SHARED BY MULTIPLE-TYPE REPAIRS [patent_app_type] => utility [patent_app_number] => 17/528248 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528248
Memory with fuse pins shared by multiple-type repairs Nov 16, 2021 Issued
Array ( [id] => 18317390 [patent_doc_number] => 11631474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Redundancy analysis method and redundancy analysis apparatus [patent_app_type] => utility [patent_app_number] => 17/508910 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508910
Redundancy analysis method and redundancy analysis apparatus Oct 21, 2021 Issued
Array ( [id] => 17463462 [patent_doc_number] => 20220076768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => TEST SYSTEM AND TEST METHOD [patent_app_type] => utility [patent_app_number] => 17/504836 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504836 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504836
Test system and test method Oct 18, 2021 Issued
Array ( [id] => 17900523 [patent_doc_number] => 20220310185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK [patent_app_type] => utility [patent_app_number] => 17/502475 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502475
Memory device with failed main bank repair using redundant bank Oct 14, 2021 Issued
Array ( [id] => 19328627 [patent_doc_number] => 12046316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Techniques for detecting a state of a bus [patent_app_type] => utility [patent_app_number] => 17/502982 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 20815 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502982
Techniques for detecting a state of a bus Oct 14, 2021 Issued
Array ( [id] => 18401942 [patent_doc_number] => 11664087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/490443 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 18164 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490443
Semiconductor device Sep 29, 2021 Issued
Array ( [id] => 17566333 [patent_doc_number] => 20220130482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => Global-local Read Calibration [patent_app_type] => utility [patent_app_number] => 17/485087 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485087
Global-local read calibration Sep 23, 2021 Issued
Array ( [id] => 18271060 [patent_doc_number] => 20230092302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SYSTEM FOR OUTPUTTING TEST DATA FROM MULTIPLE CORES AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/482151 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482151
System for outputting test data from multiple cores and method thereof Sep 21, 2021 Issued
Menu