Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17615094 [patent_doc_number] => 20220157374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH [patent_app_type] => utility [patent_app_number] => 17/666452 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666452
Periodic calibrations during memory device self refresh Feb 6, 2022 Issued
Array ( [id] => 17795334 [patent_doc_number] => 20220254426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/592512 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592512 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592512
Nonvolatile semiconductor storage device and read voltage correction method Feb 3, 2022 Issued
Array ( [id] => 18219340 [patent_doc_number] => 11594286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Non-volatile memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/665049 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665049
Non-volatile memory device and method of operating the same Feb 3, 2022 Issued
Array ( [id] => 18472745 [patent_doc_number] => 20230207033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => CONCURRENT COMPENSATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/590679 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590679
Concurrent compensation in a memory system Jan 31, 2022 Issued
Array ( [id] => 18827499 [patent_doc_number] => 11842788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Method for determining repair location for redundancy circuit, method for repairing integrated circuit, electronic device and storage medium [patent_app_type] => utility [patent_app_number] => 17/649192 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/649192
Method for determining repair location for redundancy circuit, method for repairing integrated circuit, electronic device and storage medium Jan 26, 2022 Issued
Array ( [id] => 19679111 [patent_doc_number] => 12190982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/585156 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6770 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585156
Memory and operation method thereof Jan 25, 2022 Issued
Array ( [id] => 18514395 [patent_doc_number] => 20230230650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHODS AND DEVICES FOR FLEXIBLE RAM LOADING [patent_app_type] => utility [patent_app_number] => 17/580458 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580458
Methods and devices for flexible RAM loading Jan 19, 2022 Issued
Array ( [id] => 18607890 [patent_doc_number] => 11749366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Semiconductor memory device capable of performing soft-post-package-repair operation [patent_app_type] => utility [patent_app_number] => 17/578305 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5922 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578305
Semiconductor memory device capable of performing soft-post-package-repair operation Jan 17, 2022 Issued
Array ( [id] => 18286113 [patent_doc_number] => 20230101585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Method of Determining Defective Die Containing Non-volatile Memory Cells [patent_app_type] => utility [patent_app_number] => 17/576754 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576754
Method of determining defective die containing non-volatile memory cells Jan 13, 2022 Issued
Array ( [id] => 18704491 [patent_doc_number] => 11791007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Leakage detection circuit, nonvolatile memory device including leakage detection circuit, and memory system including nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/576480 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576480
Leakage detection circuit, nonvolatile memory device including leakage detection circuit, and memory system including nonvolatile memory device Jan 13, 2022 Issued
Array ( [id] => 18154717 [patent_doc_number] => 11567695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Buffer circuit with data bit inversion [patent_app_type] => utility [patent_app_number] => 17/575524 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575524
Buffer circuit with data bit inversion Jan 12, 2022 Issued
Array ( [id] => 20317983 [patent_doc_number] => 12456538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 18/261631 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3635 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/261631
Semiconductor storage device Jan 11, 2022 Issued
Array ( [id] => 18950790 [patent_doc_number] => 11894093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Stacked DRAM device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/568649 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568649
Stacked DRAM device and method of manufacture Jan 3, 2022 Issued
Array ( [id] => 17550176 [patent_doc_number] => 20220121518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/562505 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562505
Semiconductor memory devices, memory systems including the same and methods of operating memory systems Dec 26, 2021 Issued
Array ( [id] => 18781996 [patent_doc_number] => 11823761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Pre-read in opposite polarity to evaluate read margin [patent_app_type] => utility [patent_app_number] => 17/561008 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 13608 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561008
Pre-read in opposite polarity to evaluate read margin Dec 22, 2021 Issued
Array ( [id] => 18226171 [patent_doc_number] => 20230065165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => WRITE-ASSIST FOR SEQUENTIAL SRAM [patent_app_type] => utility [patent_app_number] => 17/554838 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554838
WRITE-ASSIST FOR SEQUENTIAL SRAM Dec 16, 2021 Abandoned
Array ( [id] => 17963414 [patent_doc_number] => 20220343995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SYSTEM AND METHOD FOR PARALLEL MEMORY TEST [patent_app_type] => utility [patent_app_number] => 17/538982 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538982
System and method for parallel memory test Nov 29, 2021 Issued
Array ( [id] => 18528546 [patent_doc_number] => 11715544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => System and method for low power memory test [patent_app_type] => utility [patent_app_number] => 17/538942 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538942
System and method for low power memory test Nov 29, 2021 Issued
Array ( [id] => 17462413 [patent_doc_number] => 20220075718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Keeping Zones Open With Intermediate Padding [patent_app_type] => utility [patent_app_number] => 17/455887 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455887
Keeping zones open with intermediate padding Nov 18, 2021 Issued
Array ( [id] => 19252520 [patent_doc_number] => 20240203517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Logical Memory Repair with a Shared Physical Memory [patent_app_type] => utility [patent_app_number] => 18/556858 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18556858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/556858
Logical Memory Repair with a Shared Physical Memory Nov 16, 2021 Pending
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